Subject: Fwd: Minutes Verilog++ Meeting July 16th
From: David Kelf (davek@co-design.com)
Date: Mon Aug 06 2001 - 18:13:19 PDT
Hi again.
Here are Peter's comments on the minutes of 16th. Again, these could be
discussed in the next meeting if necessary.
Dave
>>We started the review of the docs - pages 5-20
>>Question/comments are being documented by Stu Sutherland as he is the guy
>>working on the documents in general. An overview of the comments that came
>>up were:
>>Page 7 - Possible issue around syntax of time specifications - needs further
>>discussion at end of sessions.
>>Page 7 - Real number format - is standard solid, synthesizable - use IEEE
>>nomenclature
>>Page 9 - Comment around the use of long long instead of long int. Decided
>>not to change
>>Page 10 - Can vector widths be compiler dependent - needs discussion in
manual
>>Page 10 - Definition of logic - wait to page 19.
>>Page 11 - Issues around the use of timescale across boundaries - further
>>discussion required
>>Page 14 - Possible comment required on vectored/scalared - Stu to follow up
>>with Peter Flake
Verilog compatibility issues
>>Page 14 - Slight change to deprecation note concerning integer
>>Page 14 - Nomenclature around packed versus unpacked, why even define them -
There are distinct differences in usage. Peter can explain in meeting if
necessary.
>>needs another example (foo4) in multiple array example. Page14 - Related to
>>above, concern from David S about general method used to define - Verilog
>>compatibility issues.
>>Page 14 - Issue with maximum array size specification - needs clarification
>>from Simon/PeterF - is this a vector width or an array.
>>Page 14 - Error in example at bottom - needs ';'
>>Page 15 - Third line ';' missing
>>Page 15 - Can you have two dimensional slices - needs clarification and/or
>>example
Apparently right now this is not defined.
>>Page 16 - Shouldn't use title 'discussion' in spec.
>>Page 16 - Is default one bit wire or logic - needs discussion with Peter F
Default is one bit wire - Verilog compatibility
>>Page 16 - Page formatting problem needs fixing - 'Constants' title obscured
>>Page 16 - Does 'Parameter' need adding to syntax, or should local/specparam
>>be taken out - Check with PeterF. Parameters look like they are covered
>>elsewhere.
This might be worth disussion. Have to cxonsider backwards compatibility.
>>Page 17 - Automatic tasks forward reference required - part of Verilog2K,
>>should be noted, also page 42.
>>Page 19 - Clarify what can write to a net - as per Verilog2K
>>Page 19 - Manner in which a logic variable be written - needs clarification
>>from Peter F
It looks like manual is fairly exhaustive. Need to understand where the
holes are, if any.
>>Page 19 - Change to wording of force override logic variable sentence.
>>
>>General Question - VPI Interface to new standards - yes but not focus now
>>General Question - Should we deprecate items? We will add a session towards
>>the end of the first review in September on deprecation. Stu will keep a
>>list of items.
>>
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