Subject: Re: FW: Assertions spec available for review
From: Andy Tsay (andytsay@yahoo.com)
Date: Sun Apr 14 2002 - 22:42:58 PDT
Hi,
I have some questions regarding the
design assertion subset dated April 4, 2002.
On page 4 of 11
---------------
Need specs (what do they mean) for the keywords
triggers
accept
reject
On page 4 of 11
---------------
// sync
// async
How do assertions get sync/async reset?
On page 10 of 11, in 3rd paragraph
----------------
"Note that in [n], the n must be a non-negative
literal or a constant expression."
Does the n need to be an integer type?
On page 10 of 11, in 4th paragraph
----------------
"assert (a*[0:3];b;c); // (a;b) or (a;b;a;b)Note that"
This looks like some typos.
1. The "Note that" portion shoule not be mixed
with the line comment // ...
2. The comment portion "// (a;b) or (a;b;a;b)
does not seem to go with the assertion
"assert (a*[0:3];b;c);"
On page 10 of 11, in 4th paragraph
----------------
"This means that a sequence a;ab;a;b;c; will pass."
Please explain in more details.
Is "ab" a typo in sequence a;ab;a;b;c; ?
In "Controlling Assertions"
---------------------------
Please explain the differences between
$assertoff and $assertkill
and show explicit parameters to all 3 system tasks:
$assertoff([levels [, scope1, scope2, ...]]);
$assertkill([levels [, scope1, scope2, ...]]);
$asserton([scope1, scope2, ...]);
The system tasks seem to take input parameters
in a way similar to VCD system tasks.
On page 11 of 11, in "System Functions"
----------------
"$inset(<expression>,,<expression>...)"
Is ",," a typo of "," ?
Regards,
Andy
--- Vassilios.Gerousis@Infineon.Com wrote:
> The assertion committee has approved the assertion
> constructs for SystemVerilog.
> You can download it from the link below. Please
> prepare to discuss this as well
> as Draft 6 on next conference call.
>
>
> -----Original Message-----
> From: David Lacey [mailto:dlacey@rsn.hp.com]
> Sent: Saturday, April 06, 2002 6:55 PM
> To: vlog-pp@eda.org
> Subject: Assertions spec available for review
>
>
>
> Attached you will find the current version of the
> Assertion
> Specification that will be included in the System
> Verilog spec. We
> still have some cleanup to do on the document, but
> felt that it would be
> good to get it out to the SystemVerilog group for
> review as soon as
> possible.
>
> You can find the spec at:
>
http://www.eda.org/assertion/docs/SUPERLOG_DAS_1.8_Accellera_final.pdf
>
> David and Tom
>
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