Subject: Re: $root, prototypes etc.
From: Simon Davidmann (simond@co-design.com)
Date: Mon Mar 18 2002 - 03:41:51 PST
what is this SV? if you mean SystemVerilog - please use its name long hand.
we don't write V for Verilog, so lets not use SV...
unless of course you are going to advocate using the name SVHDL. for
SystemVerilog HDL - which I would discourage :-)
Simon
At 11:12 AM 3/15/2002, Stefen Boyd wrote:
>At 10:06 AM 3/15/2002 -0800, Kevin Cameron x3251 wrote:
>> Tasks and functions without statements are considered
>> prototypes.
>
>SV has already "enhanced" them so that no statement is required.
>Take a look at the bnf.
>
>I would like to add a friendly ammendment:
>
>1) instead of "extern" let's use "import" as we've already
> got it as a reserved word with SV.
>
>2) Tasks and functions should also be explicitly imported,
> since a task or function with no statement is now
> supported... This just means allowing the import
> as a module item in addition to it's use in a modport.
>
>Regards,
> Stefen
>
>
>--------------------
>Stefen Boyd Boyd Technology, Inc.
>stefen@BoydTechInc.com (408)739-BOYD
>www.BoydTechInc.com (408)739-1402 (fax)
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