Subject: Re: comments on array proposal
From: Michael McNamara (mac@verisity.com)
Date: Thu Apr 11 2002 - 09:48:50 PDT
Paul Graham writes:
> >
> > In Verilog it is perfectly legal to index a scalar. Scalars that
> > have no dimension defined are actually treated as if they were
> > vectors, declared as:
>
> Here's a test case:
>
> module m(q, d);
> output q;
> input d;
>
> assign q = d[0];
> endmodule
>
> I have access to only two simulators:
>
> Verilog-XL:
>
> Warning! Illegal vector reference to scalar net - (d) [Verilog-IRETM]
> "test_index_scalar.v", 5:
> 1 warning
My point -- this is just a 'warning', which users ignore...
In VCS we hence supported this syntax. It is quite possible that VCS
no errors of this; I don't have access to VCS either... :-)
>
> NC-Verilog:
>
> assign q = d[0];
> |
> ncvlog: *E,NOBSOS (test_index_scalar.v,5|15): bit-select
> operator cannot be applied to scalar [4.2.1(IEEE)].
I assume this above message is an error, and not a warning?
>
> LRM 4.2.1 says:
>
> Bit-selects extract a particular bit from a vector net, vector reg,
> integer variable, or time variable.
>
> Since the LRM distinguishes between scalar and vector, and since section
> 4.2.1 specifically uses vector and not scalar in describing bit-selects, I
> conclude that a bit-select of a scalar is illegal.
>
> But to return to the main point. Even if your simulator accepts a
> bit-select of a scalar, which I agree makes a certain intuitive sense, does
> it (or will it in Verilog-2001) accept a multi-level array access of a
> scalar:
>
> assign q = d[0][0][0][0];
>
> This is analogous to asking for $left(d, 4).
>
> Paul
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