Subject: SystemVerilog 3.0 is Officially An Accellera Standard
From: Vassilios.Gerousis@Infineon.Com
Date: Mon Jun 03 2002 - 17:05:02 PDT
Dear HDL+ members,
The last vote has been counted. As of now, SystemVerilog 3.0 is an officially recognized standard by Accellera Organization. This will officially be announced tomorrow
by Accellera Chairman. The tally is as follows:
> Antrim - approve
> Avant! - approve
> Cadence - abstain
> Co-Design - approve
> Forte - Approve.
> Mentor -approve
> Motorola - Abstain
> NEC - approve
> Sun - Approve
> Synopsys - approve.
> Verisity - approve
>
> Congratulation to everyone who helped to make this possible. SystemVerilog 3.0 is now an Accellera approved standard.
>
> Best Regards
>
Vassilios
> ------------------------------------------------------------------------------------------------------------------------------
> Dr. Vassilios Gerousis Infineon Technologies
> DAT CAD, MchB
> Telephone: +49-89-234-21342 BalanSt. 73
> Fax: +49-89-234-23650 D-81541 Munich
> email: Vassilios.Gerousis@infineon.com Germany
> Site Map: http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
> ----------------------------------------------------------------------------------------------------------------------------------
>
>
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