Subject: Final SystemVerilog 3.0 LRM
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Mon Jun 03 2002 - 20:16:19 PDT
All,
The final SystemVerilog 3.0 LRM is complete. Vassilios will make copies
available in a separate e-mail. I will have hard copies for those
attending Wednesday's meeting.
I received feedback and corrections to the draft 9 document Dan Jacobi, and
Heath Chambers, plus a few things I found myself. These corrections are
NOT annotated with color or change bars in this final edition. Following
are the changes between draft 9 and this final edition.
1) Removed all references to "draft" from the LRM.
2) Added an acknowledgement page with a list of committee members as
provided by Vassilios.
3) All BNF keywords and tokens were changed from Bold-Red text to
Bold-Black text. The color is a special tag within the document source,
and is easy to change back to red when we begin working on the
SystemVerilog 3.1 drafts.
4) Section 7.8: For table 7.2 where it flows onto a new page, "(continued}"
was added to the table title.
5) Section 13.6: Indented the line a.slaveWrite; in the else branch of
module memMod.
6) Section 14.1: Changed paragraph 2, bullet 2 FROM "foo #(name=value,
name=value) u1(...);" TO "foo #(.name(value), .name(value)) u1(...);".
7) Section 18.2: Changed paragraph 5
FROM "(parameter_name=value)" TO "#(.parameter_name(value))".
8) Annex A.2.1.3: Removed the reference to state_declaration from
block_data_declaration.
9) Annex B: Added the keywords assert, assert_strobe, void.
Note: Dan also suggested a couple of BNF clarifications that apply to what
we inherited from the IEEE 1364-2001 standard. These clarifications were
not made in the SystemVerilog 3.0 document. I will forward those to the
1364 BTF reflector for that committee to correct.
Stu
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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