Subject: Invitation to Accellera's Annual DAC Breakfast & Panel
From: Dennis Brophy (dennisb@model.com)
Date: Mon Jun 03 2002 - 22:10:47 PDT
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Accellera's Annual DAC Breakfast Panel Invitation
Dear Verilog++ Committee,
I cordially invite you to attend the annual Accellera DAC breakfast
panel. The breakfast and
panel are free, but space is limited. To reserve your place, please visit
www.accellera.org/calendar.html <http://www.accellera.org/calendar.html> or
contact Lynn Horobin at Lynn@Accellera.org <mailto:Lynn@Accellera.org>
before June 4th.
After June 4th, registration is on site for any open seats.
Accellera, an electronics industry organization driving the development
of language-based
standards for electronics design, is hosting a breakfast and panel at the
Design Automation
Conference (DAC) in New Orleans ( www.dac.com <http://www.dac.com/> ).
Novilit, Inc., an emerging EDA company
providing solutions for embedded communications protocols, is co-hosting the
event, which
features a gourmet German breakfast.
To meet the needs of a rapidly expanding and changing marketplace,
today's design puzzle
requires the fitting together of large IP blocks, standard buses and
software components from
multiple sources into FPGAs, ASICs and custom ICs. Panelists will address
how
hardware/software/firmware for successful SoC design can plug and play
together.
I look forward to seeing you there.
Regards,
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Dennis Brophy, Chairman - Accellera
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When: Wednesday, June 12, 2002, 7:30am - 9:00am
Registration opens at 7:15am and presentations begin at 7:30am
Where: Marlborough Room, Riverside Hilton, New Orleans, Louisiana
Who: The meeting is open to all DAC attendees and the press
About the Panel
Topic: Plug & Play: Hardware/software/firmware flows for
successful SoC design
Moderator: Ron Wilson, Special Editor, EE Times
Host: Michael McNamara, Accellera's Vice-Chairman and Verisity's
Senior Vice President of Technology
Panelists: ARM Ltd., Ian Phillips, Principal Staff Engineer
Cisco Systems, Sean W. Smith, Lead Verification
Engineer
Novilit, Axel Tillman, Chairman & CEO
STMicroelectroincs, Philippe Magarshack, Vice
President, Design
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Automation, Central R&D Group
Sun Microsystems, Shrenik Mehta, Sr. Engineering
Manger, Global
Testability, Tools and Validation
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