Subject: Re: Proposal: Implicit Port Instantiation in SystemVerilog
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon Dec 17 2001 - 11:42:58 PST
Hi, Kev -
This explanation is starting to help.
True that .* covers one level of downward connection.
Do I understand correctly that the following is covered by Verilog-AMS
inherit/export?
Top module - has an "export" net Vcc connected to a power pad on the Top module
Middle module - has no Vcc port and no Vcc net but has an instantiated leaf
module, "A"
Leaf module, "A" - has a Vcc "inherit"-port, ignored by the Middle module,
but connects upward and finds the "export" net in the Top module and makes
the connection
In the above design, if the Top module is missing the export keyword, a
syntax error would be reported? As you say, "inherit" must find a
corresponding "export" so modules don't freely and unexpectedly inherit a
net in a higher module. The "export" keyword is the documentation that we
expect the exported net to be potentially inherited elsewhere in the design
(but not specifically noted which module(s) can inherit the net).
I believe "inherit" ports would be ignored by the .* implicit port
connection proposal. Seems like inherit/export are almost a completely
separate proposal, but should be considered and then document that .*
ignores "inherit nets."
Is this the idea? Could you give a useful simple example of a simple but
real circuit that would use this construct?
The light bulb is turning on but I need some help to power the filament!
Regards - Cliff
At 11:05 AM 12/17/01 -0800, Kevin Cameron x3251 wrote:
>The .* syntax covers downward declared connection (any input
>in the child can be connected to [?]). "Inherit" would handle
>upward connection, i.e. when a module is instantiated with signals
>declared with inherit you would search straight up the instance
>hierarchy until you find a matching exported signal. The keyword
>"inherit" would be required (and would be like "input" syntactically),
>and the keyword "export" is desirable to avoid false connection in
>modules that are unaware of inheritance.
>
>Since inheritance skips levels in the hierarchy, it may be worth
>using the "export" syntax for the same purpose downwards since the
>.* syntax only works over a single port boundary, e.g. any signal
>declared "export" would match an otherwise unbound port of the same
>name in lower levels (not declared "inherit").
>
>NB: my main reason for wanting this is kind of thing is for the
>connection of signals like Vdd/Vss, substrate and thermal modelling
>connections that are left off logic/RTL modules but are needed by
>analog models of library cells in a mixed analog/digital flow. How
>useful it is in general I'm not sure.
>
>Regards,
>Kev.
//*****************************************************************//
// Cliff Cummings Phone: 503-641-8446 //
// Sunburst Design, Inc. FAX: 503-641-8486 //
// 14314 SW Allen Blvd. E-mail: cliffc@sunburst-design.com //
// PMB 501 Web: www.sunburst-design.com //
// Beaverton, OR 97005 //
// //
// Expert Verilog, Synthesis and Verification Training //
//*****************************************************************//
This archive was generated by hypermail 2b28 : Mon Dec 17 2001 - 11:43:08 PST