Subject: issues for next telcon
From: Stefen Boyd (stefen@boyd.com)
Date: Mon Dec 17 2001 - 12:03:03 PST
Vassilios,
There are a couple things that we should make sure
we have clarified in the next Accellera SystemVerilog
meeting.
1) It seems that the rules for always_comb are not
completely clear in the document. I remember
(possibly Nov 5 call) agreement that there would
be a static (ie not simulation runtime) requirement
of all tools to ensure that the logic in always_comb
is truly combinational. The current language (draft 3)
has weak language that doesn't make that restriction
clear: "SystemVerilog has special always blocks which allow additional
checking:"
"allow" should be "include" or "require"
Also, the last paragraph is too weak. It doesn't make
it clear that all tools have to provide a complete
check to ensure that the logic is combinational. If the
static check is to difficult in the general case, we
need restrictions to make it feasable.
Peter Flake mentioned in his Dec 5 email
that always_comb can't have timing control... which
should be incorporated into the document.
Peter also mentioned in his Nov 10 email regarding
the minutes, that the restrictions for always_comb
and always_latch would include the bodies of function
calls, but not tasks.
2) There doesn't seem to be any discussion in the document
on what happens with mismatched connections to modules.
We need to make sure it's documented what happens when
you try to connect a wire to a structure, or what decides
the value of a logic variable that connects the logic
variable outputs from two modules, real ports to logic,
etc. Trying to decide these rules is what kept structures
out of the 1364-2001 standard, so we want to benefit from
what Co-design has done in this area also...
Regards,
Stefen
--------------------
Stefen Boyd Boyd Technology, Inc.
stefen@BoydTechInc.com (408)739-BOYD
www.BoydTechInc.com (408)739-1402 (fax)
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