Subject: Port connection in general
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Thu Apr 11 2002 - 18:40:33 PDT
A thought for 3.1:
There are a bunch of extensions in Verilog-AMS which are applicable if you
want to be able to connect ports of different types e.g. a signal of type "real" to
a port of "logic [63:0]". Verilog-AMS uses "disciplines" as a typing mechanism
to determine what A/D conversion blocks need to be inserted between the
drivers and receivers of the signals on a mixed net, SystemVerilog could use
typedefs in a similar way e.g.:
typedef logic [63:0]fpbus;
typedef real fltval; // 64 bit IEEE
connect b2r output fltval, input fpbus; // use function or module b2r to convert
connect f2b output fpbus, input fltval;
fltval function b2r (input fpbus data_in);
return $bitstoreal(data_in);
endfunction
fpbus function r2b(input fltval data_in);
return $realtobits(data_in);
endfunction
- I used functions here rather than modules (which AMS uses) because the
conversion doesn't need to save state. If a driver of a signal is of type fltval
and it gets connected to a receiver of type fpbus an r2b function would be
inserted.
Note: conversion is part of driver resolution in AMS (if you do it properly) and is
nothing like the port-bound conversion functions in VHDL (which should be avoided
at all cost) - see http://www.eda.org/verilog-ams/htmlpages/vams_obj.pdf for details
on disciplines and multi-domain signal resolution. In the example above the type
'logic []' has higher accuracy than real, so resolution gets performed in that domain
(if there are multiple drivers).
Kev.
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