Subject: FW: SystemVerilog vote
From: Vassilios.Gerousis@Infineon.Com
Date: Sat Jun 01 2002 - 15:43:16 PDT
FYI
I feel that everyone needs to see again the editorial comments from Cadence and my response. I am tired of this continued bad image on our committee and our work.
We still have two companies that did not vote Cadence and Sun. Hopefully they will do this on Monday.
On Tuesday, I will send you the final results.
Vassilios
-----Original Message-----
From: Gerousis Vassilios (CL DAT)
Sent: Sunday, June 02, 2002 12:33 AM
To: accellera_bod@accellera.org
Subject: RE: SystemVerilog vote
I have no problems with vote that Cadence has casted against SystemVerilog. I do have a problems again with editorial comments that Cadence have repeatedly shown. They do not reflect the real image and trying to distort the good image of TCC as well as SystemVerilog. Maybe they are meant in an innocent way but this has been repeated multiple times. I am not amused.
I am still amazed after our discussions with Cadence engineers at the last Verilog++ to see continuing negative editorial comments from Cadence representative. I had to respond on some of the negative comments provided by Grant below.
1- The bad image of "outstanding technical issues" is a continual attack on the image of SystemVerilog 3.0. There are some technical issues, but SystemVerilog provides an excellent standard that advances Architectural design through the interface section, it advances the verification technology through assertions as well enhancement of many language capability to enable better verification and high level of abstraction. As the chairman of Verilog++ I am offended on this repeated bad image casted by Cadence. The committee have done its best job in producing a great LRM and we have made the decision to stop at a certain stage and publish the LRM for usage. This decision was voted and agreed by everyone. We do plan to address "some" of the issues and also add enhancement to continue our evolution of SystemVerilog.
2- Again the "Standard Coordination" reflect that I and my chairs are not doing our Job. When we started SystemVerilog assertion, Sugar was not even in the picture. FVF was still discussing which language to choose. In addition Sugar has not even come out its technical debate from the committee member. I and the chairs are addressing coordination that makes sense. Asking to make VHDL and Verilog to have the same syntax does not make sense. Doing a coordination on semantics as well how much increase we need to improve SystemVerilog in assertion is part of our chairs discussion. We as the chairs of Accellera will provide the board with a sensible roadmap, and not just based on an input of a single company.
3- To attack SyetmVerilog again as not driven by users requirements is again a shameful remarks. Let me remind everyone that almost 50% of HDL+ committee is made up of users. On The Verilog++, we have all users/consultants that use Verilog and build designs (six IEEE committee members). Infineon which is a growing Verilog user, represented by myself, National representative and also LSI logic. This 9 people out of the current SystemVerilog 3.0 committee which is about 20. On the assertion side we have HP, LSI logic, CISCO, Intel, SGI. Of course the fact that Co-design with real commercial product in this area, cannot survive without actual users that has helped in defining this wonderful language. This a proven product, and not just have been cooked in a standard organization.
One final remark the SCOPE was agreed by the Accellera one year ago. The committee has worked hard in analyzing every corner of the language. 90% of the issues were generated by the other members of the committee. All of the members of the committee have accepted this even. I do not understand, why Cadence continues on this path produce this bad propaganda.
Best Regards
Vassilios
-----Original Message-----
From: Grant Martin [mailto:gmartin@cadence.com]
Sent: Wednesday, May 29, 2002 6:30 PM
To: accellera_bod@accellera.org
Subject: SystemVerilog vote
Cadence formally abstains from the SystemVerilog vote.
Due to issues with the SystemVerilog 3.0 specification, briefly re-iterated
below, we feel that it is premature for the Accellera board to vote on this
proposal.
However, notwithstanding our absention, and regardless of how the vote of
the board turns out, I would like to reinforce our commitment to be a fully
participating member of the SystemVerilog committee, and the proposed '3.1'
process, in order to help rectify the issues we and others have raised.
Issues with SystemVerilog 3.0 (draft 8 and 9):
------------------------------------------------------------------
1. Outstanding Technical Issues. Several concerns about the existing
document have been voiced by various members of the HDL+ Verilog Design
Extensions Technical Sub-Committee, including Cadence. These include
issues about type system extensions, for example. Cadence has sent initial
feedback to the committee, and Erich Marschner will send any additional
concerns to the committee email reflector by the end of the week, as
requested by Vassilios.
2. Standards Coordination. The syntax and semantics of assertions in the
HDL+ extensions and the syntax and semantics of assertions in Sugar
conflict with each other at several points. We believe that these conflicts
should not be propagated into the final version of either standard,
because they would create user confusion and diminish the usability of both.
3. Scope of Extensions. We feel that the SystemVerilog extensions for RTL
design, test bench development, and for system level design, need to be
reviewed to ensure that they are the best choices to meet user requirements.
Regards
Grant Martin
------------------------------------------------------------------------------------------------------
Grant Martin
Fellow, Cadence Labs tel. +1-510-647-2804
Cadence Design Systems mobile +1-510-703-7470
2001 Addison Street, Third Floor fax. +1-510-486-0205
Berkeley, California 94704 U.S.A. email gmartin@cadence.com
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