Subject: Re: "universal" logic type
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Fri Jan 18 2002 - 17:44:55 PST
> From owner-vlog-pp@server.eda.org Fri Jan 18 16:19:32 2002
>
> I would like the logic type to truly be a
> universal type that replaces the need for wire
> and reg. Basically, I'm proposing what I thought
> the logic type provided when I first was introduced
> to it.
>
> In it's current form, the logic type is very
> similar to a reg except for two major differences:
> 1) Two modules share a logic variable just
> like two always blocks in a module share
> a reg (assuming the logic type connects
> through ports).
> 2) A single continuous assignment can use a
> logic variable instead of a wire.
>
> I would like to propose the following for the
> logic type to make it truly universal:
> 1) If the logic variable is driven by more
> than one source, it will be resolved as
> a wire (strength resolution). This
> includes continuous assignments and
> primitives.
> 2) It's an error to attempt to drive a value
> onto a logic variable AND perform a
> procedural assignment.
> (I'm assuming that module port connections
> that are all logic types will use the same
> shared variable behavior as currently used
> for the logic type. Module port connections
> to a reg or wire will be treated as continuous
> assignments and thus require wire styled
> multiple driver resolution).
>
> Stefen
I prefer to break these things down into simulator
basics: there are processes, drivers and nets. Processes
assign values to drivers which are resolved to provide
a value for the net.
The difference between a 'reg' and a 'wire' declaration
is that with 'reg' the processes in a module share a driver
rather than having seperate drivers.
Continuous assignments and primitives are degenerate
cases where only a single process and driver are present.
The implication in Draft 3 for the 'logic' variable is that
it is like a 'reg' with global scope, i.e. all processes
share the one driver. In which case for consistency with
'reg' you would want to disallow continuous assignment.
But personally I think the semantic restriction that you
can't do a continuous assign to a register is arbitrary
and could be waived for logic types, i.e. a 'logic'
variable could be the target of multiple continuous
assigns - and the last one sticks as with procedural
assignments. Trying to work out if you have both continuous
and procedural assignments could be non-trivial in
implementation so I'd rather avoid the necessity.
Kev.
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