Subject: Re: "universal" logic type
From: Peter Flake (flake@co-design.com)
Date: Sun Jan 20 2002 - 08:06:21 PST
Stefen,
While your proposal looks interesting, it would create a language
anomaly. The behavior of the logic type would differ from other data types
such as real, not only because of the resolution but also because the
number of values would change depending on whether strengths were
required. From the simulation efficiency point of view, it is useful to
confine strengths to wires and limit logic and reg to two bits.
Peter.
At 04:11 PM 1/18/02 -0800, Stefen Boyd wrote:
>I would like the logic type to truly be a
>universal type that replaces the need for wire
>and reg. Basically, I'm proposing what I thought
>the logic type provided when I first was introduced
>to it.
>
>In it's current form, the logic type is very
>similar to a reg except for two major differences:
> 1) Two modules share a logic variable just
> like two always blocks in a module share
> a reg (assuming the logic type connects
> through ports).
> 2) A single continuous assignment can use a
> logic variable instead of a wire.
>
>I would like to propose the following for the
>logic type to make it truly universal:
> 1) If the logic variable is driven by more
> than one source, it will be resolved as
> a wire (strength resolution). This
> includes continuous assignments and
> primitives.
> 2) It's an error to attempt to drive a value
> onto a logic variable AND perform a
> procedural assignment.
> (I'm assuming that module port connections
> that are all logic types will use the same
> shared variable behavior as currently used
> for the logic type. Module port connections
> to a reg or wire will be treated as continuous
> assignments and thus require wire styled
> multiple driver resolution).
>
>Stefen
>
>
>--------------------
>Stefen Boyd Boyd Technology, Inc.
>stefen@BoydTechInc.com (408)739-BOYD
>www.BoydTechInc.com (408)739-1402 (fax)
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