Subject: Re: "universal" logic type
From: Alec Stanculescu (alec@fintronic.com)
Date: Mon Jan 21 2002 - 10:31:16 PST
> Sender: owner-vlog-pp@eda.org
> Precedence: bulk
>
> I would like the logic type to truly be a
> universal type that replaces the need for wire
> and reg. Basically, I'm proposing what I thought
> the logic type provided when I first was introduced
> to it.
>
> In it's current form, the logic type is very
> similar to a reg except for two major differences:
> 1) Two modules share a logic variable just
> like two always blocks in a module share
> a reg (assuming the logic type connects
> through ports).
> 2) A single continuous assignment can use a
> logic variable instead of a wire.
>
> I would like to propose the following for the
> logic type to make it truly universal:
> 1) If the logic variable is driven by more
> than one source, it will be resolved as
> a wire (strength resolution). This
> includes continuous assignments and
> primitives.
It will probably have to include connections to bi-directional
transistors, as well.
> 2) It's an error to attempt to drive a value
> onto a logic variable AND perform a
> procedural assignment.
> (I'm assuming that module port connections
> that are all logic types will use the same
> shared variable behavior as currently used
> for the logic type. Module port connections
> to a reg or wire will be treated as continuous
> assignments and thus require wire styled
> multiple driver resolution).
>
> Stefen
>
>
> --------------------
> Stefen Boyd Boyd Technology, Inc.
> stefen@BoydTechInc.com (408)739-BOYD
> www.BoydTechInc.com (408)739-1402 (fax)
>
Question: what is the advantage of not giving a special name (wire or
reg) to a an object which we know will be used in a certain way. The
more information we can capture in a declarative way the better of we
are (in general:-).
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