Subject: Re: Proposal: Deprecate procedural assign-deassign
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Tue Oct 30 2001 - 10:15:33 PST
At 02:22 PM 10/29/01 -0800, Kevin Cameron x3251 wrote:
> > Subject: Re: Proposal: Deprecate procedural assign-deassign
> >
> > I also agree.
> > --Steve Grout
>
>I seem to remember that the current methodology for driving the
>resolved value onto signals from auto-inserted A/D conversion modules
>in Verilog-AMS is something like an assign from procedural code
>(I'm not sure how anyone is actually implementing it).
>
>If it's to be deprecated can we extend force/release to have some
>kind of optional strength/priority to cover the functionality
>needed in A/D converters etc?
>
>Kev.
Can anyone from the Verilog-AMS team shed light on the above statement?
In Verilog-1995 and -2001, procedural assign statements are made to
variable types (such as regs or reals) and variable types do not have
strengths. Only net types have strengths.
The procedural assign statement also does not resolve with other procedural
assign statements. In Verilog, last procedural assign statement wins and
takes control of the variable until another procedural assign statement
makes an assignment or until a deassign statement, which causes the
assigned variable to hold its last assigned value until the next normal
procedural assignment changes the variable. Truely 'tis an ugly construct!
Did Verilog-AMS change this behavior? Am I missing something in this
discussion?
Regards - Cliff
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