Subject: Re: VOTE - Two Deprecation Proposals - Votes due Wed., April 17
From: Michael McNamara (mac@verisity.com)
Date: Tue Apr 16 2002 - 14:16:44 PDT
Stuart Sutherland writes:
>
> I vote YES to #1, deprecating defparam
>
> I vote NO to #2, deprecating procedural assign/deassign. I feel there are
> rare circumstances where this construct models functionality that is
> needed. I feel force/release is not a suitable substitute, as it is solely
> intended as a verification and debug construct. I have done benchmarks
> (albeit a long time ago) that show assign/deassign provide significantly
> better simulation performance than can be obtained using procedural
> assignments. I think that as we push to higher levels of abstracts--the
> aim of SystemVerilog--there may be new and appropriate and not yet thought
> of uses for assign/deassign. The only reason assign/deassign are not used
> at the RTL level is because Synopsys chose not to support the deassign
> portion in synthesis. At least one other synthesis tool, Synergy, did
> support assign/deassign, but alas, that tool never gained enough market
> share to set the de facto synthesizable subset. Still, Synergy proved that
> assign/deassign can be realized in logic.
>
> Stu
Just a comment: I implemented the force/release and assign/deassign
features in VCS, and they use the exact same mechanism, and the same
speed.
There is nothing you can do with assign/deassign that you can't do
with force/release; but there is much you can do with force/release
that can not be done with assign/deassign.
>
> At 12:36 PM 4/15/2002, Clifford E. Cummings wrote:
> >E-MAIL VOTES - DUE BY END OF DAY ON WEDNESDAY, APRIL 17TH
> >
> >Any person who has attended three of the last four SystemVerilog committee
> >meetings or 75% of all of the SystemVerilog committee meetings is eligible
> >to vote.
> >
> >All eligible SystemVerilog committee members should separately vote "yes,"
> >"no" or "abstain" on the following TWO proposals (see attached file).
> >
> >PROPOSAL #1 - Deprecate defparam
> >PROPOSAL #2 - Deprecate procedural assign & deassign
> >
> >Regards - Cliff
> >
> >
> >
> >
> >//*****************************************************************//
> >// Cliff Cummings Phone: 503-641-8446 //
> >// Sunburst Design, Inc. FAX: 503-641-8486 //
> >// 14314 SW Allen Blvd. E-mail: cliffc@sunburst-design.com //
> >// PMB 501 Web: www.sunburst-design.com //
> >// Beaverton, OR 97005 //
> >// //
> >// Expert Verilog, Synthesis and Verification Training //
> >//*****************************************************************//
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Stuart Sutherland Sutherland HDL Inc.
> stuart@sutherland-hdl.com 22805 SW 92nd Place
> phone: 503-692-0898 Tualatin, OR 97062
> www.sutherland-hdl.com
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
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