Subject: Re: Using iff example - very bad coding style!
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Dec 11 2001 - 14:57:05 PST
Good afternoon all;
Cliff writes:
>True. As with most race conditions in Verilog, if the designer is
>careful
I have never met a careful enough designer. They always make mistakes
that take time to discover and fix. I would more like to see
elements added to verilog to make it faster for people to develop
workable code.
This element may have some relevance for verification code, or
modeling code, but it just does not work for modeling registers.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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