Subject: Verilog++ 12th Committee Meeting Minutes (Face to Face)
From: Simon Davidmann (simond@co-design.com)
Date: Mon Nov 12 2001 - 09:18:59 PST
Verilog++ 12th Committee Meeting
November 12th, 2001
Vassilios leading. Simon taking minutes
Attendees
(a-aaaaaaaaaa) Vassilios Gerousis *
(-aaarar-aaaa) Dave Kelf
(--aaa--aaaa) John Sanguinetti
(a----ra-aaa-) John Emmitt *
(aaa--a-aa---) Dennis Brophy *
(aaaaaaaaaaaa) Stu Sutherland *
(------aaaaa) David Knapp
(aaaraaar-aaa) Tom Fitzpatrick *
(raa-aaaaaaa-) Phil Moorby (rep Peter Flake) *
(aaa-aaaaaaaa) Anders Nordstrom *
(a--a-aaaaaa) Cliff Cummings
(araaa-aaaaaa) Simon Davidmann *
(a-----aaaa--) Harry Foster *
(a-aaaaa-a-aaa) Stefen Boyd *
(aaaaaaaaaaaa) David Smith *
(aa--a-a--aa-) Mike McNamara *
(aaaaa) Kevin Cameron *
(-aa-a) Andy Tsay
(a) Steve Pollock *
(a) Prakash Narain *
Review Charter of HDL+
----------------------------------------
Key issue is to focus to ensure that we have Accellera first release of
Verilog-ACE for DAC 2002.
This will include ESS but will include Assertions syntax if that syntax is
provided to the committee by mid Dec 2001.
Will need Accellera board approval in April to release for DAC2002
deliverables - ESS, OVL, Assertion syntax, and maybe deprecation list
DAC Goal - deliverables
------------------------------------
OVL
library
OVL Semantic Reference Manual
Verilog-ACE document known as Verilog-ACE 2002?
ESS
Assertions
Timelines
vote on Assertions requirements doc this week
proposed Assertions extensions in Jan time frame - syntax can start to be
reviewed then
people who want to be involved in detailed language review of assertions
syntax need to join assertions committee
Verilog++ committee needs to focus on closing down discussion on ESS (still
to do interfaces) and agree on Draft 2.
this will free people up to focus on the assertions.
so May 1st is deadline for our final documents, no revisions after that point
so before May 10th HDL+ will need to approve and propose to BoD
so need May 10th 2002 will need to give to BoD documents to approve
will submit to Accellera BoD to approve as Accellera Standard
then we will be position to publicize at DAC
Review ACE draft 2
----------------------------
$root was discussed - yes it can lead to spaghetti code, but - it enables
design to be started without defining the modules/netlist
and so should be included - we need to add an example of usefulness.
Discussed interfaces - looks good, need more discussion on the example in
the document.
Name Change
---------------------
Proposal is that this verilog extension work is called SystemVerilog 3.0
This was voted and approved annonymously
ie so the project name is not going to be Verilog-ACE - but SystemVerilog 3.0
verilog 0.0 = Verilog 85
1.0 - IEEE verilog95
2.0 - IEEE verilog2001
3.0 - ESS+assertions
4.0 will include other things like OO, verification
Deprecation
------------------
Cliff to look at the list and process of how we can create a list to give
to the IEEE to propose
Paper at HDLcon
-------------------------
Peter/Simon/Tom to write paper on SystemVerilog Interfaces - comparing - in
SystemC session
Actions:
-------------
Stu had lots to change and made notes himself.
Vassilios - increase reflector bottleneck on email size on
vlog-pp,assertion@eda.org to 1.2Mbyte
Peter - must define attributes on modports section 6.2
Peter - section 9.3 state machine encoding needs to be put in - so suggest
wording and bnf
Peter - 10.6 add some explanation of what process buys in terms of the
pipeline example.
Peter - $root - need example of why it is useful - section 12.2
Peter - port connections for multi dimensional instance arrays - section 12.8
Peter - section 12.10 - add more about type versus instance names
Peter - Interfaces: need to get some voice recording of Peter explaining
the examples for Stu, or Peter needs to write much more explanation
Cliff - need to maintain the deprecation list
Next Meeting 26th November by phone.
ACE Draft 2 Still to do:
--------------------------------
BNF discussion
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