Re: Verilog++ 11th Committee Meeting Minutes

Subject: Re: Verilog++ 11th Committee Meeting Minutes
From: Peter Flake (flake@co-design.com)
Date: Sat Nov 10 2001 - 06:02:44 PST

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Hi all,

At 03:06 PM 11/5/01 -0500, Dave Kelf wrote:

Anders: Can regular always or always @* be used in P37 2nd paragraph -
comment required

Replace with:

As well as the state declaration, Verilog ACE uses the transition statement in procedural code.

DavidS: State machine example status in 9.2.
Action Peter: Other examples have been provided in an email of Oct 8th.
Timing example and possibly example with async reset still required.

Word doc attached.

Anders: P43, Section 10. Are four lines after word "discussion" struck out,
relevant to processes. Needs statement to clarify.
Action Peter: Write statement on this.

In an always block which is used to model combinational logic, forgetting an 'else' leads to an unintended latch.
To avoid this mistake, specialized always_comb and always_latch blocks are provided, which indicate the design intent to synthesis and formal verification tools. These blocks treat functions called as part of the block, and therefore the sensitivity list and restrictions are extended into the functions called. Note that this does not apply to tasks.

Anders: P44, Section 10.3. Always_comb block. Should state that it is
illegal to read a variable before written? Andy: Need to say every variable
must be written before read. Strengthen statement. Stu will send wording
change to Cliff for quick review.

Cliff: Section 10.4. Wording should be improved. Impose restriction that
only one event control can be used in the always block.
Action Peter: Add wording and send to Stu.

always_ff p4: @(posedge clock iff reset == 0 or posedge reset) begin r1 <= reset ? 0 : r2 + 1; .... end

The always_ff block imposes the restriction that only one event control is allowed.

Stu: Explanation of the ability to place a range on a port.
Action Peter: Provide one sentence and example showing this.

The BNF has a bug. It should read:

<port_type> ::= <data_type>

| <net_type> [<signing>] {<packed_dimension>}

| 'event'

My apologies for the lateness of the reply. I am travelling.

Peter.

application/msword attachment: FSM_3.doc

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