Subject: DeCSS Verilog Source WITH FSM -- Convert to SystemVerilog ?
From: Vassilios.Gerousis@Infineon.Com
Date: Wed Feb 20 2002 - 07:16:14 PST
Hello Vlog-ppers,
http://www-2.cs.cmu.edu/~dst/DeCSS/Gallery/DAH/
contains source code for DeCSS
with state machine. Could someone examine it and see if SystemVerilog Can help in improve its size and abstraction level. It is small, but can provide interesting comparison on an actual circuit.
Vassilios
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