Subject: RE: Some Action Items To Formalize Our Discussions and voting for next meeting
From: Vassilios.Gerousis@Infineon.Com
Date: Fri Feb 15 2002 - 02:25:21 PST
Hello Everyone,
I am forwarding this email again for people to read more closer. This
email was sent on February 5 (10 days ago), asking for issue owners to start
formalizing the issues.
My assumption is that several of you are busy working on HDLCON/DATE
or both.
Since we have a holiday in the USA, and since none of you has responded. I guess
we will have our conference as scheduled in the minutes, February 25. Topics for February 25 meeting will be:
1- Discussion on this process outlined below.
2- Review any document that we receive by that time. If none, it will be a short meeting.
3- Status of Draft 4, and the plan for HDLCON distribution.
a- Printing copies and handing it during registration (HDLCON).
4- Preparation for Verilog++ and HDL+ meeting on March 14 at Mentor Graphics.
Best Regards
Vassilios
> -----Original Message-----
> From: Gerousis Vassilios (CPD DAT)
> Sent: Tuesday, February 05, 2002 3:24 PM
> To: 'vlog-pp@eda.org'
> Subject: Some Action Items To Formalize Our Discussions and voting for next meeting
> Importance: High
>
> Hello Everyone,
> It looks like the committee decided not to have a conference next week. Since
> it almost an entire month, I would like to formalize the issues list. We should follow
> a similar route like it is done in IEEE. I want to target our next formal meeting for voting decisions.
> to do this, we need to summarize each issue, and document its status. For Each issue we should have a description of the following:
>
> 1- Name of The Issue.
> 2- Name of the proposal / Issue.
> 3- small description.
> 4- Assigned Owner.
> 5- Analysis From Language Experts (IEEE team and Co-design).
> 6- Status : Open, postponed or closed.
> 7- Voting for or against.
>
> Definition of Issues are:
> 1- Disagreement of current capability, feature, semantic or construct. ($root, FSM, etc.). Stu
> has been doing for each LRM draft on smaller items.
> 2- Incomplete section (like Interface section).
> 3- Enhancement: e.g. .*, inheritance (export/import), assertion (April delivery from assertion group).
> 4- Finalizing BNF (Alec should get the BNF of 2001 so that we can get his feedback).
>
>
> I would like to ask every person who has an open issue as described above to prepare a page for our review on February 18. On February 25 we will discuss the final status and we will decide to do voting or not.
>
> Action items:
> 1- Document Issues.
> 2- Final review on February 18.
> 3- Possible voting to include or remove certain things based on the status.
>
> Please correct on the following or any of the above:
>
> 1- $root (Boyd).
> 2- FSM (Cliff).
> 3- *. (Cliff).
> 4- Completion of Interface (Dave Kelf).
> 5- BNF (Stu), analysis should be done by Alec.
> 6- Inferred declaration, Inheritance (David Smith).
> 7- Anders (All issues are closed, if not, then please revive it).
> 8- FSM enhancements (we heard few from Alec and Adam).
> 9- Deprecating item (by end of April, this matter will be closed for SystemVerilog Standard Release). Currently, there are ideas but not documented or discussed.
> 10- Paul (I believe your issues raised are closed, if not, please document).
>
> I hope that the majority should examine and critic this and hopefully provide
> us with the issue list.
>
> 1- February 18: we will review these list and ensure their accuracy in terms of analysis and
> ownership. This is a special meeting just to ensure that all issues are well documented.
> 2- February 28: We will start evaluating each issue and vote, if we have enough data.
> 3- March 13 or 14: our face to face meeting for HDL+, with report from assertion and Verilog++ and to synchronize again our milestones. We will spent the rest of the time discussing Draft 4, what is missing and continue the issue list.
>
> We must formalize this process and we also must formalize the analysis.
>
> Best Regards>
>
> Vassilios
> ------------------------------------------------------------------------------------------------------------------------------
> Dr. Vassilios Gerousis Infineon Technologies
> DAT CAD, MchB
> Telephone: +49-89-234-21342 BalanSt. 73
> Fax: +49-89-234-23650 D-81541 Munich
> email: Vassilios.Gerousis@infineon.com Germany
> Site Map: http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
> ----------------------------------------------------------------------------------------------------------------------------------
>
>
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