Subject: Re: SystemVerilog draft 6 - structs,unions & packing.
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Fri Apr 26 2002 - 13:17:52 PDT
[ I'm having trouble reading your mail can you send as "plain text & html" ?]
>Peter Flake wrote:
>
>Kevin,
>
>Since there are existing Verilog simulators, I think it is unrealistic to demand changes to their data structures.
Ah, but isn't Superlog/SystemVerilog doing that anyway?
>Currently the PLI specification sets constraints e.g. tf_nodeinfo.
That doesn't appear to cover multi-dimensional data for starters, and there is no implication that
it gives you access to the raw simulation data - it doesn't constrain anything.
>I think your suggestion of an alignment control may be useful, but I propose that it should be a tool-specific
>feature which could be supplied by the >attribute mechanism. For example
>(* alignbits=32, little_endian *)
>typedef struct packed {
> bit [15:0] count ;
> bit enable;
>} Ctrl; // match compiled alignment
>
>Peter.
If you are suggesting everyone should interpret the attributes the same way then it
should be part of the language proper, and if you are suggesting it's optional then
designs will not be portable.
If no-one is prepared to commit to stating the default alignment and packing for
SystemVerilog at this time then we should strike unions from the LRM, there
isn't enough specification for a common implementation.
Kev.
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