Subject: List of 3.1 Items
From: Dave Kelf (davek@co-design.com)
Date: Fri Apr 26 2002 - 16:05:58 PDT
Hi Everyone,
I had an action to review all the correspondence and meeting minutes, and
come up with a list of items for which it was agreed that the discussion
should be deferred to SystemVerilog 3.1.
Here is the list based on every email where I could spot a potential item.
Note that in some of these cases we had made decisions, but it appeared
more work was required and had been proposed for 3.1.
Please review this carefully. Feel free to either add items that I might
have missed, or clarify issues. Note that this is not a set in stone list,
but an attempt at starting a schedule of items to be discussed. I am sure
there will be more and we can add these as the committee sees fit.
Cheers
Dave
Cliff, Aug01 - Deprecation - recommendations made in 3.0, but we need to
decide how much further to take this and if their are other items
David S, Aug01 - Time precision and timescale in general - did we finally
settle this?
Kevin, Sep01 - Data Channels (seems similar to interfaces - this may have
been based on a mis-understanding)
Stu, Simon, Sep01 - Pointers
Kevin, Oct01 - Force Release extensions for strength etc, if
assign/deassign is to be deprecated
General, Nov01 - State Machines - need to be re-examined
Kevin, Nov01 - Extern modules - connected with $root discussion
Vassilios, Nov01 - Object Orientation
Paul, Dec01 - Datapath enhancements. Although work was done on this I want
to make sure we captured everything
Alec, Dec01 - consideration for interfacing to "foreign" languages - e.g. VHDL
Kevin, Mar02 - Alias capability - or port jumpers - may have been covered
in inout
From March face to face meeting
Inheritance and Inferred Declarations
Hierarchical and multi-clock FSMs
Kevin, Mar02 - Dynamic process naming and control
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