Subject: Proposal to Delete the new SystemVerilog FSM syntax
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Nov 29 2001 - 15:13:19 PST
Hi, All -
Attached is a pdf document with proposals to scrap the new state machine
syntax that has been proposed for the SystemVerilog language.
I have spent two days trying make the new state machine syntax work with
all of the FSM styles that I have used in Verilog without much success. I
found that the new syntax offered very little advantage while imposing yet
another coding style with serious limitations.
The attachment will probably be the basis for a future conference paper,
either pointing out the reasons not to abandon existing Verilog FSM coding
styles or just as a good paper pointing out the pros and cons of different
Verilog coding styles, so your feedback would be appreciated.
Sorry I did not discover these problems sooner.
Regards - Cliff
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