Subject: Re: Proposal to Delete the new SystemVerilog FSM syntax
From: Stefen Boyd (stefen@boyd.com)
Date: Thu Nov 29 2001 - 16:31:40 PST
At 03:13 PM 11/29/2001 -0800, Clifford E. Cummings wrote:
>Attached is a pdf document with proposals to scrap the new state machine
>syntax that has been proposed for the SystemVerilog language.
Cliff,
Thanks for spending the time to try using the new syntax
with some existing problems... I must agree that the new
transition statement seems to lack when trying to do
asynchronous resets and one-hot.
Some comments on your notes:
1) "Upon closer examination, I am confused by the always_comb statement."
It looks like you're talking about FSM1. This is the
same as we have been doing with two always blocks: the
"state" declaration includes the "@(posedge clk)" to
create the sequential logic, and the always_comb
creates the combinational next-state logic. The problem
is that we really need to be able to handle asynchronous
reset here in order to truly get the two always block
equivalent...
2) "I believe there is a missing semi-colon in the third transition statement:"
According to the bnf (d3 p87):
<statement> ::=
...
| <transition_to_state> <statement_or_null>
Looks to me like it's treated the same as delay or
event control that is allowed to have a statement
immediately following.
3) "I suggest using the more Verilog-like Boolean tests as opposed to the more
VHDL-like equal comparisons,"
I agree!
Regards,
Stefen
--------------------
Stefen Boyd Boyd Technology, Inc.
stefen@BoydTechInc.com (408)739-BOYD
www.BoydTechInc.com (408)739-1402 (fax)
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