Tested Interface Examples

Subject: Tested Interface Examples
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon Feb 25 2002 - 08:57:49 PST

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Hi, All -

Interface proposal reminders:
E-mail sent on 12/17/2001 by Vassilios: Subject: FW: Interface Section
Modification Proposals - 20011217
E-mail sent on 12/13/2001 by Cliff: Subject: Proposal: Implicit Port
Instantiation in SystemVerilog

Attached are syntactically correct models for:

Section 13.2.1
Section 13.2.2
- Interface model
- Interface model with .name port connections
- Interface model with .* port connections
Section 13.2.3
- Interface model
- Interface model with .name port connections
- Interface model with .* port connections

Before I go off and re-code and compile all of the models in this section,
I want to make sure the work I a doing is consistent with the expectations
of the committee.

Regards - Cliff

• application/octet-stream attachment: ex_13_2_1.slg

• application/octet-stream attachment: ex_13_2_2.slg

• application/octet-stream attachment: ex_13_2_2a.slg

• application/octet-stream attachment: ex_13_2_2b.slg

• application/octet-stream attachment: ex_13_2_3.slg

• application/octet-stream attachment: ex_13_2_3a.slg

• application/octet-stream attachment: ex_13_2_3b.slg

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