Subject: arrays in SystemVerilog
From: Paul Graham (pgraham@cadence.com)
Date: Mon Feb 25 2002 - 08:04:34 PST
Sorry for being so late with comments on arrays, but better late than
never...
I still don't understand the point of distinguishing between packed and
unpacked arrays, except to maintain backwards compatibility with verilog.
Is it possible for a typedef to declare an unpacked array dimension? For
instance, I might want to declare an array of structs. Yet the syntax for
data_type in section 3.2 says that the dimensions specified in a data_type
are packed dimensions:
<data_type> ::= ... | <type_identifier> { <packed_dimension> }
It is possible to assign a whole array if all its dimensions are packed, but not
possible to assign a whole array with unpacked dimensions. Why not?
Arithmetic operations are allowed for packed arrays. Even for
multidimensional packed arrays? For instance:
wire [3:0][7:0] x, y, z;
assign z = x + y;
Does this treat x and y as 32-bit integers and then add them? Or does it
independently add corresponding 8-bit fields of x and y?
Why not rationalize arrays as follows:
1. Eliminate the packed array syntax, except to allow a single dimension to
the left of the declarator, to remain compatible with verilog.
2. If you want some way of specifiying an efficient, packed representation,
using the existing keyword 'vectored'.
3. Allow reading and assigning of full arrays.
4. Allow constant part selects of arrays.
5. Arithmetic operations can be allowed on arrays by defining them to act on
corresponding words.
Paul
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