Subject: RE: Moving Ahead on SystemVerilog 3.1 Despite Politics
From: Vassilios.Gerousis@Infineon.Com
Date: Thu Jun 20 2002 - 06:28:23 PDT
Only chairs are allowed to this. If you want to change this, then I
suggest that make a motion to the Accellera board to allow you to attend.
-----Original Message-----
From: Simon Davidmann [mailto:simond@co-design.com]
Sent: Thursday, June 20, 2002 3:09 PM
To: vlog-pp@eda.org; assertion@eda.org
Cc: accellera_bod@accellera.org
Subject: Fwd: Moving Ahead on SystemVerilog 3.1 Despite Politics
Importance: High
Vassilios - you need to start being a little more honest in your politics.
Nobody has started any negative campaigns apart from you personally to me - which I would respectfully suggest you stop.
Everybody, as far I can tell is intent on moving Verilog forwards - we all just have differences of opinions as to its direction and process - and surely as a technical leader you should be exploring peoples views and not trying to shut them up. The Accellera Board that provides you with your position as Technical Chair expects you to do this.
Regarding your discussion with the chairs today - I hope you are following Accellera policy of giving appropriate people fair notice of meetings and ensuring they can attend. We must ensure that all policies and guidelines are followed.
Also I think it would be appropriate for the Accellera Board Members to be invited to such a meeting as it sets the direction of Accellera - which ultimately is the Boards prerogative.
Please let me know when the meeting is to be held/phone numbers etc.
Thanks Vassilios.
And for your information - the proposal you submitted to the Accellera Board to form the Verilog++ committee dated feb 28, 2001 clearly shows the Verilog++ as the main committee - which has now become called HDL+ - and so Verilog++ and HDL+ are one and the same committee - with Dave Kelf as co-chair - in fact it is the SystemVerilog committee that is below the Verilog++ committee - as the Verilog++ committee includes the OVL.
Also - your foils are technically wrong - you have no authority to re-write a committees charter - the rules state that it is voted on by the members of the committee
1) the HDL+ committee's goals are 'Verilog++ is focused on extending VerilogHDL to higher domains of abstraction. It will include a subcomittee to extend both Verilog language and VHDL with assertions.
5) donation policy is not set by Technical Chair and Accellera Chairman - please re-read the Accellera rules - there are very comprehensive rules and your simple bullet is completely wrong. A committee must request a donation before any Accellera board member is authorized to accept one. No committee minutes have stated that any committee has requested a donation in the SystemVerilog space. I would suggest you do not violate Accellera rules.
6) as the enhancement committee has not met, it can not have set any requirements let alone have requested any donations - thus this is clearly incorrect statements
we already have committees that look into C/C++ APIs - the Accellera ITC committee - they should investigate if any C/C++ API donations are needed
we already have a formal committee - and they should investigate if we want a Vera donation into Accellera.
- if you do not do this - then you are instigating a full blown assertions war - and the Accellera Board will not endorse this
we must stick to the Accellera Rules Vassilios - you must ensure that we all do - nobody should be violating the rules - it is your responsibility as Accellera Board appointed Technical Chair - that you personally ensure that people do not violate Accellera's committee rules.
8) on donation - this does not comply at all with the current Accellera Board approved rules - if you follow this - you will be breaking the rules.
9) voting rules - designates are allowed.
11) it is not you personally that sets the goals - as the rules state - each committee sets it own goals
it is the committees that can look in to donations and look at other ones if they so wish. - as happened in the Formal committee.
14) formal - there is nothing wrong with multiple languages - the formal committee has repeatedly said they do not want one language - they want one to be verilog flavor, one vhdl, etc etc - it is the formal committee that should make this call - that is what they have spent the last 3 years working on. It is not the TC that can just change direction here.
15) - now this is better - put Vera into the formal committee and let them work with it. - this is what I think the 30 members of the formal group and 10 members of the Assertions committee would want.
Vasilios - what is all this - George Orwell's 1984?? - you are rewriting history!!! -
please stick to the Accellera's Board agreed rules and do not violate them.
You are trying to make too many changes here to the rules and that requires a board meeting to do.
Clearly the Accellera Members interests are not being served by what is currently going on.
Simon
X-MindSpring-Loop: accellera_bod@accellera.org
From: Vassilios.Gerousis@infineon.com
To: accellera_bod@accellera.org
Subject: Moving Ahead on SystemVerilog 3.1 Despite Politics
Date: Thu, 20 Jun 2002 13:21:40 +0200
X-Mailer: Internet Mail Service (5.5.2653.19)
Sender: owner-accellera_bod@accellera.org
Delivered-To: co-design.com-1@easyalias.easynet.co.uk
I am still working despite continued and increasing politics (you know who).
I am attaching a set of slides that will be discussed today with my chairs. Assigning
members to these new subcommittees have started. We will establish milestones and
targets.
Since some people has started negative campaigns, I am showing positive signs to move forward. Every bad move by politics, I will show a positive attitude to continue. See my slides.
Best Regards
Vassilios
<<HDL+Chairs-meeting.ppt>>
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