Subject: Re: Enumerated Types Proposals
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Mon Apr 08 2002 - 13:57:35 PDT
At 12:39 PM 4/8/2002, Clifford E. Cummings wrote:
>We still need to comment on what should happen if an unassigned enum name
>follows an enum name with x or z assignments. Is this a syntax error or do
>names S1 and S2 take on consistent defined values?
>
>// IDLE=2'b00, XX=2'bx, S1=??, S2=??
>enum {IDLE, XX='x, S1, S2} state, next;
I think it should be an error. The enumerated value should increment, and
the normal arithmetic rules of Verilog are 2'b0x+1 is 2'bxx, and 2'b0z+1 is
2'bxx.
A previous x or z value may can have a defined behavior for special
enumerations, such as enum_onehot, when and if we define custom enumerated
types for SystemVerilog 3.1. These special types will use something other
than an increment of the previous value.
Stu
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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