Subject: RE: SystemVerilog vote
From: Vassilios.Gerousis@Infineon.Com
Date: Mon Jun 03 2002 - 11:59:32 PDT
Hello Erich,
I do appreciate the feedback and your honesty. Believe me, I did not start this. First Cadence tried to delay SystemVerilog voting process, then many announcement by cadence started appearing and finally the editorial comments. It is hard for me today, to distinguish between political and purely technical actions after you put the different puzzle together. I have no intention of discouraging any person who wants to contribute for the benefit of SystemVerilog or any Accellera standard committee.
Paul has been a valuable addition to our team since March of 2002 (maybe earlier). His input was great help. Paul is a valuable member and he voted to accept SystemVerilog 3.0 to go Accellera. If Cadence has problem internally to communicate, this is not a problem with me, or my committee or Accellera. This also should not be taken as a chance trying to re-define what SystemVerilog has accomplished for the last year either. Cadence email, clearly shows such an indication.
In the last committee meeting, I thought we addressed the concern of your team (Paul and you) and I thought we do plan to move forward. If you remember, I have asked the committee and specifically you and Paul, multiple time, to see if there are still issues. I thought we agreed on the target for 3.1. Your email below said that. However, as you can see, I was NOT pleased to see the editorial comments and the special adjectives that accompanied Cadence vote.
I was not surprised that Cadence voted to abstain, but I was surprised with the continual criticism of SystemVerilog standard, of the committee and how the TCC works. As a technical community, we can discuss and come to a conclusion based on technical facts. But I do not accept unfounded and continual criticism of our committee and its output. How many tools in market get release that is free of bugs and lack certain features? As an EDA vendor you have very good experience in this area. An EDA vendor, at a certain point must make the decision to stop and release the tool after internal debate. We did the same thing with SystemVerilog, we stopped, we debated on a technical basis with the best information we had and we released. To abstain, or vote against SystemVerilog just because there is a list of issues, is not working as part of a team. To continue bashing SystemVerilog and present a false image is also not working as a team.
I welcome every Cadence expert to come and work. I know several of them and their contribution will be valuable. This need to be pure and without political motives. The several emails I have seen and different directions that Cadence has taken publicly over the last month is questionable in my mind. Let us examine the fact that Cadence announced a product development based on Sugar. Sugar is not Accellera standard yet and is currently going through the refinement process. However, one of the reason given for not voting for SystemVerilog is due to synchronization between Sugar (have not left the committee yet) and SystemVerilog which has completed and today is the in final Accellera board voting process. Sugar can be changed to be compatible with SystemVerilog and the large legacy of Verilog IP.
Again, I welcome Cadence engineers to participate on a purely technical basis. Paul has provided excellent input and helped to shape the array constructs within SystemVerilog. I consider this as a valuable contribution, and I hope for similar contribution by the new members. I do not hide my opinions, and I want to make sure that everyone must work as a team. That is why I appreciate your email. Your email has confirmed to me that Cadence engineers want to participate on a technical basis and not for political reason. I am sure that this confidence will be increased as we move along with the committee goals and targets.
Again, thank you.
Best Regards
Vassilios
-----Original Message-----
From: Erich Marschner [mailto:erichm@cadence.com]
Sent: Monday, June 03, 2002 7:34 PM
To: Vassilios.Gerousis@Infineon.Com
Cc: vlog-pp@eda.org; assertion@eda.org; Grant Martin
Subject: RE: SystemVerilog vote
Vassilios,
I would like to respond to your continuing disparagement of Cadence's input regarding the System Verilog 3.0 document, to set the record straight.
1. Part of Cadence (Ambit, represented by Paul Graham) has been involved with the System Verilog committee for some time (since early 2002). Paul voted to approve the System Verilog 3.0 document, along with many others in the committee. Subsequent to that vote, Paul identified some issues that were later raised. We have agreed to defer those issues to discussion in the 3.1 effort.
2. Despite Ambit's involvement, Cadence is a big company, and there are other divisions (e.g., SFV) that have other points of view. It is true that, for various reasons, those other divisions did not get involved with the System Verilog committee until recently. However, during the past 6 months, it has become evident that more of Cadence should be involved in this activity, due to both Accellera Board encouragement and customer requests. We are now doing so.
3. Cadence intends to participate going forward with much more complete representation of its various divisions. Paul Graham continues to represent Ambit and the synthesis perspective. Steve Sharp represents the NC-Sim team and Verilog simulation. Stuart Swan represents the System-Level Design division and the system design/verification perspective. I represent the group working on transaction- and assertion-based verification in Cadence.
4. The additional people are NOT an attempt to "pack" the voting, but rather an attempt to adequately represent the different organizations within Cadence. Therefore the comment in your most recent email:
> As more people from a single company keeps coming,
> we will have a different voting rules than what we have
> done to make SystemVerilog 3.0 an Accellera Standard.
> This will be presented at the meeting. If you plan to help
> you are welcome. If you plan to slow the progress, please
> do not try.
is entirely inappropriate. In any case, we expect the System Verilog committee to follow standard Accellera voting rules, which allow only one vote per member company no matter how many representatives are present.
5. There seems to be a general attitude in your comments that participation in this committee requires general suspension of all critical faculties, and you seem to equate debate and difference of opinion with disloyalty. This does not seem to be a productive approach to developing a standard that must work well for a wide variety of users and implementors. If you want Cadence - and for that matter, any other interested party - to participate freely to help craft a robust standard, then you must respect our right to voice an opinion, whether or not it is in agreement with your own.
Regards,
Erich Marschner
Cadence Design Systems
-------------------------------------------
Erich Marschner, Cadence Design Systems
Senior Architect, Advanced Verification
Phone: +1 410 750 6995 Email: erichm@cadence.com
Vmail: +1 410 872 4369 Email: erichm@comcast.net
| -----Original Message-----
| From: Vassilios.Gerousis@Infineon.Com
| [mailto:Vassilios.Gerousis@Infineon.Com]
| Sent: Saturday, June 01, 2002 6:43 PM
| To: vlog-pp@eda.org; assertion@eda.org
| Subject: FW: SystemVerilog vote
|
|
| FYI
| I feel that everyone needs to see again the editorial
| comments from Cadence and my response. I am tired of this
| continued bad image on our committee and our work.
|
| We still have two companies that did not vote Cadence
| and Sun. Hopefully they will do this on Monday.
| On Tuesday, I will send you the final results.
|
| Vassilios
|
| -----Original Message-----
| From: Gerousis Vassilios (CL DAT)
| Sent: Sunday, June 02, 2002 12:33 AM
| To: accellera_bod@accellera.org
| Subject: RE: SystemVerilog vote
|
|
| I have no problems with vote that Cadence has casted
| against SystemVerilog. I do have a problems again with
| editorial comments that Cadence have repeatedly shown. They
| do not reflect the real image and trying to distort the good
| image of TCC as well as SystemVerilog. Maybe they are meant
| in an innocent way but this has been repeated multiple
| times. I am not amused.
|
| I am still amazed after our discussions with Cadence
| engineers at the last Verilog++ to see continuing negative
| editorial comments from Cadence representative. I had to
| respond on some of the negative comments provided by Grant below.
|
| 1- The bad image of "outstanding technical issues" is a
| continual attack on the image of SystemVerilog 3.0. There
| are some technical issues, but SystemVerilog provides an
| excellent standard that advances Architectural design
| through the interface section, it advances the verification
| technology through assertions as well enhancement of many
| language capability to enable better verification and high
| level of abstraction. As the chairman of Verilog++ I am
| offended on this repeated bad image casted by Cadence. The
| committee have done its best job in producing a great LRM
| and we have made the decision to stop at a certain stage and
| publish the LRM for usage. This decision was voted and
| agreed by everyone. We do plan to address "some" of the
| issues and also add enhancement to continue our evolution of
| SystemVerilog.
|
| 2- Again the "Standard Coordination" reflect that I and my
| chairs are not doing our Job. When we started SystemVerilog
| assertion, Sugar was not even in the picture. FVF was still
| discussing which language to choose. In addition Sugar has
| not even come out its technical debate from the committee
| member. I and the chairs are addressing coordination that
| makes sense. Asking to make VHDL and Verilog to have the
| same syntax does not make sense. Doing a coordination on
| semantics as well how much increase we need to improve
| SystemVerilog in assertion is part of our chairs discussion.
| We as the chairs of Accellera will provide the board with a
| sensible roadmap, and not just based on an input of a single company.
|
| 3- To attack SyetmVerilog again as not driven by users
| requirements is again a shameful remarks. Let me remind
| everyone that almost 50% of HDL+ committee is made up of
| users. On The Verilog++, we have all users/consultants that
| use Verilog and build designs (six IEEE committee members).
| Infineon which is a growing Verilog user, represented by
| myself, National representative and also LSI logic. This 9
| people out of the current SystemVerilog 3.0 committee which
| is about 20. On the assertion side we have HP, LSI logic,
| CISCO, Intel, SGI. Of course the fact that Co-design with
| real commercial product in this area, cannot survive without
| actual users that has helped in defining this wonderful
| language. This a proven product, and not just have been
| cooked in a standard organization.
|
| One final remark the SCOPE was agreed by the Accellera one
| year ago. The committee has worked hard in analyzing every
| corner of the language. 90% of the issues were generated by
| the other members of the committee. All of the members of
| the committee have accepted this even. I do not understand,
| why Cadence continues on this path produce this bad propaganda.
|
| Best Regards
|
| Vassilios
|
| -----Original Message-----
| From: Grant Martin [mailto:gmartin@cadence.com]
| Sent: Wednesday, May 29, 2002 6:30 PM
| To: accellera_bod@accellera.org
| Subject: SystemVerilog vote
|
|
| Cadence formally abstains from the SystemVerilog vote.
|
| Due to issues with the SystemVerilog 3.0 specification,
| briefly re-iterated
| below, we feel that it is premature for the Accellera board
| to vote on this
| proposal.
|
| However, notwithstanding our absention, and regardless of
| how the vote of
| the board turns out, I would like to reinforce our
| commitment to be a fully
| participating member of the SystemVerilog committee, and the
| proposed '3.1'
| process, in order to help rectify the issues we and others
| have raised.
|
| Issues with SystemVerilog 3.0 (draft 8 and 9):
| ------------------------------------------------------------------
| 1. Outstanding Technical Issues. Several concerns about the existing
| document have been voiced by various members of the HDL+
| Verilog Design
| Extensions Technical Sub-Committee, including Cadence.
| These include
| issues about type system extensions, for example. Cadence
| has sent initial
| feedback to the committee, and Erich Marschner will send any
| additional
| concerns to the committee email reflector by the end of the week, as
| requested by Vassilios.
|
| 2. Standards Coordination. The syntax and semantics of
| assertions in the
| HDL+ extensions and the syntax and semantics of assertions in Sugar
| conflict with each other at several points. We believe that
| these conflicts
| should not be propagated into the final version of either standard,
| because they would create user confusion and diminish the
| usability of both.
|
| 3. Scope of Extensions. We feel that the SystemVerilog
| extensions for RTL
| design, test bench development, and for system level design,
| need to be
| reviewed to ensure that they are the best choices to meet
| user requirements.
|
| Regards
| Grant Martin
|
| -------------------------------------------------------------
| -----------------------------------------
| Grant Martin
| Fellow, Cadence Labs tel. +1-510-647-2804
| Cadence Design Systems mobile +1-510-703-7470
| 2001 Addison Street, Third Floor fax. +1-510-486-0205
| Berkeley, California 94704 U.S.A. email gmartin@cadence.com
|
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