Subject: External Module Definitions
From: Kevin Cameron -Linux x3251 (Kevin.Cameron@nsc.com)
Date: Tue Nov 06 2001 - 18:35:26 PST
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0006/index.html
One difference between the analog and digital simulators is that
analog simulators often come with a unique set of primitive
models. Also, if a the module is implemented outside Verilog it
is useful to know that at compile time. Attributes on the the
external module definition would indicate where to locate it etc,
The "external module" stuff is part of a larger scheme to make
representation-stops more flexible, i.e. different tools need
different levels of detail: synthesis works down to RTL/Gate, Logic
simulation down to Gate/Switch, and analog down to transistors,
resistors etc. A goal in Verilog-AMS is to get one source description
to work for all uses, just using `ifdef/`include is not useful because
tools that can use multiple views simultaneously can be more efficient,
e.g. an AMS simulator could use a logic view to get initial conditions
for the state of the individual transitors.
Regards,
Kev.
-- mailto:Kevin.Cameron@nsc.com http://www-galaxy.nsc.com/~dkc/
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