Subject: Re: SystemVerilog draft 6 - structs,unions & packing.
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Mon Apr 29 2002 - 09:43:11 PDT
Peter Flake wrote:
> Kevin,
>
> > >Since there are existing Verilog simulators, I think it is unrealistic to demand changes to their data structures.
> >Ah, but isn't Superlog/SystemVerilog doing that anyway?
>
> No, it is adding new data types. In fact, anyone with an existing mixed
> Verilog/VHDL simulator has probably got most of the data types and
> operators already.
That makes an assumption that "union" is compatible with existing implementations.
> ......
> >
> >If no-one is prepared to commit to stating the default alignment and packing for
> >SystemVerilog at this time then we should strike unions from the LRM, there
> >isn't enough specification for a common implementation.
> >
> >Kev.
>
> It is true that SystemVerilog code using unpacked unions may not be
> portable. Does this mean that they are not useful?
>
> Peter
Templates in C++ are useful, but a real pain if you want to move code from one
compiler to another because there isn't a common implementation.
If the construct is not implementable in a portable manner I suspect that it will
be more trouble than it is worth.
Kev.
This archive was generated by hypermail 2b28 : Mon Apr 29 2002 - 09:45:07 PDT