Subject: RE: Final Reminder For Joining SV committees
From: Erich Marschner (erichm@cadence.com)
Date: Tue Jul 02 2002 - 23:14:51 PDT
Vassilios,
Can you clarify what you mean by "The assertion will be modified next"?
Do you mean that the email reflector "assertion@eda.org" will no longer work? If so, am I correct in assuming that there will be a new email reflector, and that anyone who has asked to be involved with the System Verilog assertions work going forward will be on that reflector?
Or do you mean that the System Verilog Assertions subcommittee will no longer exist? If so, what new committee will be working on System Verilog assertions?
Regards,
Erich
-------------------------------------------
Erich Marschner, Cadence Design Systems
Senior Architect, Advanced Verification
Phone: +1 410 750 6995 Email: erichm@cadence.com
Vmail: +1 410 872 4369 Email: erichm@comcast.net
| -----Original Message-----
| From: Vassilios.Gerousis@Infineon.Com
| [mailto:Vassilios.Gerousis@Infineon.Com]
| Sent: Wednesday, July 03, 2002 2:03 AM
| To: vlog-pp@eda.org
| Subject: Final Reminder For Joining SV committees
|
|
| Hello Everyone,
| This email reflector will soon disappear after this
| week. Please sign up to the other sub-committees for
| SystemVerilog (SV-BC, SV-EC, SV-CC). The assertion will be
| modified next.
|
| Thanks
|
| Vassilios
|
| -------------------------------------------------------------
| -----------------------------------------------------------------
| Dr. Vassilios Gerousis Infineon Technologies
| DAT
| CAD, MchB
| Telephone: +49-89-234-21342 BalanSt. 73
| Fax: +49-89-234-23650 D-81541 Munich
| email: Vassilios.Gerousis@infineon.com Germany
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| str%2E;HNR=73
| -------------------------------------------------------------
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