Subject: Re: An Open Process
From: Simon Davidmann (simond@co-design.com)
Date: Thu Jun 20 2002 - 11:48:47 PDT
Karen
and all those who see this - I suggest you take care and read this email.
>Please allow Vassilios and the committees to proceed with their work,
>business as it has been in Accellera (and previously OVI) according to the
>published TC guidelines, until such time as the board passes any motions to
>change existing processes.
the problem is that the rules and guidelines are not being followed - and
this is my issue
the committees want to do their work and are being currently undermined -
see the emails being sent on the subject:
about Vassilios' process:
>>On reflection it seems there is a flaw in the way Accellera manages
>>overlaps between it's various technical activities. It looks as though
>>the whole of the technical activities are donator-driven rather than by
>>users or by identified need, with the consequence there will certainly be
>>conflicting and competitive donations across technical committees. The
>>mechanism for detecting these early and resolving them in a timely and
>>effective fashion seems to be either missing or reliant on the good
>>nature of individuals which seems to me to be quite unrealistic.
this is the type of sentiment in the committees;
>>The time has come to stop accepting donations, for deficiencies to be
>>fixed and enhancements added to the selected language and for vendors to
>>put Sugar-based tools in the hands of users so we can begin to address
>>the verification crisis that is staring the electronics industry in the face!
and this about the Verilog++ meeting on 5th June and Vassilios' behavior.
>In my eight years of work, and sometimes spirited debate, on the IEEE
>Verilog committees, I have never witnessed outbursts and behavior similar
>to those exhibited in Wednesday's meeting by any committee member, let
>alone the committee chair.
and this too about Vassilios' comments about the Verilog++ meeting on 5th June
>Your statement that we, the HDL+ committee, decided to dissolve the
>Verilog++ committee during the 5 June 2002 HDL+ committee meeting is not
>correct. I was present, in person, for the entire 8 hour HDL+
>meeting. At no time did I hear any discussion of dissolving the Verilog++
>committee. This observation is collaborated in the minutes, which contain
>no record of such a discussion. The discussion was to create
>subcommittees within the Verilog++ committee, in order to more quickly
>review and develop road maps on what should go into SystemVerilog 3.1.
>
>I did not, do not, and will not vote in favor of, or endorse in any way,
>any motion to break the overall definition for SystemVerilog 3.1 into
>multiple, disparate committees. It only makes sense to me to keep the
>definition of SystemVerilog under a single committee--the Verilog++
>committee that defined it to begin with. Subcommittees under that single
>parent make sense. Disparate committees with no parent would be a mistake.
pls don't try to wash over the real issues that the committee members are
concerned about - the committees want to make progress but Vassilios
somehow wants to break all the rules and do what he personally wants rather
than the will of the committee members.
we must follow agreed rules, guidelines to retain the respect of the industry
if individuals can just control things as they see fit - then Accellera
will have no respect and will be ignored.
surely you do not want this.
Simon
At 10:59 AM 6/20/2002, Karen Bartleson wrote:
>Simon,
>
>I have resisted getting involved in this until now, but I am compelled to
>reply. The board did not agree that Vassilios would await the outcome of
>any investigations. I recall stating that this would slow down progress of
>the committees. The board agreed to investigate, but did not agree to halt
>progress in the meantime.
>
>Please allow Vassilios and the committees to proceed with their work,
>business as it has been in Accellera (and previously OVI) according to the
>published TC guidelines, until such time as the board passes any motions to
>change existing processes.
>
>Accellera has the respect of the industry for an effective standardization
>process. Our customers (yours, mine and all Accellera members) are anxious
>for standards to improve their design flows. Let's not stall progress
>while political issues are discussed.
>
>Regards,
>Karen
>
>At 08:19 AM 6/20/02 -0700, Simon Davidmann wrote:
> >Vassilios - you are not following the rules here.
> >
> >1) donations must be requested by committees
> >2) committees must meet and discuss things and vote in subsequent meetings
> >3) forming of committees can only be approved by the board
> >
> >In the Board meeting last week - which you attended - it was agreed by the
> >Board that you would await the outcome of the investigation into voting,
> >processes, committees before moving forward.
> >
> >As none of the above have been followed what you are doing now has no
> >sanction from the Accellera Board of Directors, is in clear violation of
> >its rules, and so please refrain.
> >
> >It seems we will have to elevate these issues to the next Accellera Board
> >meeting.
> >
> >I believe that SystemVerilog is a fundamental core to the work of
> >Accellera, its many committees, its public perception, and its direction
> >and the creation of committees etc needs to be discussed at the Board level
> >with the Board - as per the rules - and so yes please invite the Board to
> >your TCC meetings.
> >
> >Also - as
> >Simon
> >
> >
> >At 07:41 AM 6/20/2002, Vassilios.Gerousis@Infineon.Com wrote:
> >>Hello Everyone,
> >> I am sending alot of my times trying to get SystemVerilog 3.1 up
> >>and running. I have sent you slides that outline what I propose to happen.
> >>My chairs and I need should be given few days and we will start the
> >>activities.
> >>So please have patience.
> >>
> >>1- We will agree on a plan for action with my chairs.
> >>2- Each committee will start meeting and planning.
> >>3- Assigned donations is being prepared in PDF in small sizes so that
> >>we can send each one to the appropriate committee.
> >> a- Synopsys was asked to provide smaller chapters to be sent to
> >> designated
> >> committee. By Friday, I will send an electronic version.
> >> b- New additional donations must be discussed with me ASAP.
> >>4- We will resolve the issues as we go on. But please help me instead of
> >>putting blocks
> >>in front me. Give an opportunity, and if I am not fair, then scream at me.
> >>5- My chairs have the additional responsibility to outline how we will
> >>synchronize SystemVerilog Assertions with Sugar. Harry Foster and Erich
> >>Marschner will help
> >>in this matter.
> >>
> >> So I ask, pretty please to give me a chance to get this rolling
> >> ASAP and getting
> >>most issues resolved instead of increasing it.
> >>
> >>Best Regards
> >>
> >>Vassilios
> >>--------------------------------------------------------------------------
>----------------------------------------------------
> >>Dr. Vassilios Gerousis Infineon Technologies
> >> DAT CAD, MchB
> >>Telephone: +49-89-234-21342 BalanSt. 73
> >>Fax: +49-89-234-23650 D-81541 Munich
> >>email: Vassilios.Gerousis@infineon.com Germany
> >>Site Map:
> >>http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
> >>--------------------------------------------------------------------------
>--------------------------------------------------------
> >
> >
>___________________________________________________________________
>Karen Bartleson
>Director, Quality and Interoperability
>Synopsys, Inc.
>phone: 719-528-5467 (Colorado Springs, CO)
>fax: 719-533-0209 (Colorado Springs, CO)
>phone: 650-584-4840 (Mountain View, CA)
>fax: 650-584-4102 (Mountain View, CA)
>mobile:719-330-6727 (anywhere, USA)
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