Subject: [dkc@galaxy.nsc.com: Re: Clarification to section 3.5 - user-defined types.]
From: Paul Graham (pgraham@cadence.com)
Date: Thu Apr 11 2002 - 11:24:52 PDT
Kevin,
You sent this to me, I think you meant to send it to vlog-pp.
Paul
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Date: Thu, 11 Apr 2002 11:18:27 -0700 (PDT)
From: Kevin Cameron x3251 <dkc@galaxy.nsc.com>
To: pgraham
Subject: Re: Clarification to section 3.5 - user-defined types.
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> From owner-vlog-pp@eda.org Thu Apr 11 10:37:44 2002
>
> > > generate if (exp)
> > > typedef int T;
> > > else
> > > typedef shortint T;
> > > endgenerate
> > > T i; // data type depends on exp
> > >
> > > Regards,
> > >
> > > Peter.
> >
> > That doesn't look very legal to me - I would have expected the definition
> > of T to expire at the endgenerate.
>
> You're assuming that something declared in a generate statement lives in the
> "scope" of the generate statement. But a generate statement does not create
> a scope. Only named begin/end blocks (and modules and subprograms) create
> scope. So if the example were coded:
>
> generate if (exp)
> begin: block1
> typedef int T;
> end
> else
> begin: block2
> typedef shortint T;
> end
> endgenerate
>
> then you would be correct in saying that the declaration T "expires" within
> the generate statement.
>
> I know what you're going to say -- this doesn't make modular compilation any
> easier. Lookup of *local* symbols can't be done by the parser, since the
> symbol table, even for symbols local to the module, is not complete until
> generate statements have been elaborated.
>
> Paul
Actually it makes modular compile nigh impossible, so since typedefs are
SystemVerilog rather than Verilog2000 I'd recommend making typedefs illegal
in generate statements - no need to make things worse than they already are.
Anyone got an example (without the typedef) that actually works?
Kev.
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