Subject: Re: Proposal to Delete the new SystemVerilog FSM syntax
From: Michael McNamara (mac@verisity.com)
Date: Wed Dec 05 2001 - 07:09:57 PST
Peter Flake writes:
> Hi, Cliff
>
> To answer your questions:
>
> The always_comb does (and should not) have any timing controls and so does
> not wait except at the beginning.
>
> In the event of the reset going high and then low, the nonblocking state
> assignment will schedule a reset then cancel it.
The above seems un hardware like, assuming the reset pulse is not so
short that it would not be sensed by the gate.
>
> The difference between ->>S0 and ->> S.S0 is that the first is only valid
> in a transition(S) statement, since the names are local to the state machine.
>
> Yes a begin-end pair is needed for multiple statements. Which is why the
> abbreviation
> ->>S0 if( )...;
> has been devised to shorten
> begin ->> S0; if( ) ...; end
>
> Peter.
>
> At 03:13 PM 11/29/01 -0800, Clifford E. Cummings wrote:
> >Hi, All -
> >
> >Attached is a pdf document with proposals to scrap the new state machine
> >syntax that has been proposed for the SystemVerilog language.
> >
> >I have spent two days trying make the new state machine syntax work with
> >all of the FSM styles that I have used in Verilog without much success. I
> >found that the new syntax offered very little advantage while imposing yet
> >another coding style with serious limitations.
> >
> >The attachment will probably be the basis for a future conference paper,
> >either pointing out the reasons not to abandon existing Verilog FSM coding
> >styles or just as a good paper pointing out the pros and cons of different
> >Verilog coding styles, so your feedback would be appreciated.
> >
> >Sorry I did not discover these problems sooner.
> >
> >Regards - Cliff
> >
> >
> >
> >
> >//*****************************************************************//
> >// Cliff Cummings Phone: 503-641-8446 //
> >// Sunburst Design, Inc. FAX: 503-641-8486 //
> >// 14314 SW Allen Blvd. E-mail: cliffc@sunburst-design.com //
> >// PMB 501 Web: www.sunburst-design.com //
> >// Beaverton, OR 97005 //
> >// //
> >// Expert Verilog, Synthesis and Verification Training //
> >//*****************************************************************//
>
>
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