Re: Parameter Interface Bugs?? Clarification?? Enhancement??


Subject: Re: Parameter Interface Bugs?? Clarification?? Enhancement??
From: Michael McNamara (mac@verisity.com)
Date: Wed Jan 09 2002 - 11:33:04 PST


I also favor 7.

I am intrigued with 8; but am hesitant because I do believe that the
somewhat redundant inclusion of the word 'parameter' (as required by
7) will be very helpful to a user who encounters such usages only
occasionally, and likely in a large module definition supplied by a
library vendor.

Stuart Sutherland writes:
> Precedence: bulk
>
>
> I think the only correct answer in regards to the current 1364-2001
> standard is that the syntax for the placement of commas and semicolons
> should exactly match the syntax of port declarations with the port list. I
> believe that is #7 in Cliff's long list of examples. The requirement to
> have " ;, " in the parameter list, as in #3, is inconsistent with the ANSI
> C style port lists, and should be documented as an errata in the current
> 1364-2001 BNF.
>
> As for the inclusion of localparams in the module parameter list, that
> should be postponed for a consideration in a future revision to the
> standard. Perhaps it could be added with SystemVerilog, or perhaps in
> 1364-200x, or perhaps not at all. In any case, I feel it is not an errata
> in the current BNF.
>
> Stu
>
> At 10:45 AM 1/9/2002, Clifford E. Cummings wrote:
> >Precedence: bulk
> >
> >Hi, All -
> >
> >This is a separate email thread to discuss parameter interface bugs,
> >enhancements, etc.
> >
> >In a separate thread, there is a discussion about whether or not
> >localparam would be a valuable addition to a parameter list. One of the
> >stronger arguments against adding localparam to a parameter interface is
> >that a localparam cannot be modified during instantiation; therefore, it
> >is not really part of an interface. An argument in favor is that the
> >calculation of a localparam may be necessary before making ANSI-port
> >declarations.
> >
> >If we do decide to add localparams to a parameter interface, a reasonable
> >restriction may be to require all localparam declarations to be placed
> >after all parameter declarations in a parameter interface.
> >
> >Opinion and vote (please indicate which of the following parameter
> >interface forms that you believe are or should be legal in Verilog-2001 or
> >SystemVerilog (the BNF does not support some of these and it requires
> >others that did not seem to be intended - oops!)
> >
> >(1) module mymodule #(parameter DEPTH=16; parameter WIDTH=8) (...) //
> >semicolons between parameters
> >
> >(2) module mymodule #(parameter DEPTH=16; parameter WIDTH=8;) (...) //
> >semicolons after all parameters, including the last parameter
> >
> >(3) module mymodule #(parameter DEPTH=16;, parameter WIDTH=8;) (...) //
> >semicolons after all parameters and commas after semicolons between parameters
> >
> >(4) module mymodule #(parameter DEPTH=16, parameter WIDTH=8) (...) //
> >commas between parameters / parameter keyword repeated
> >
> >(5) module mymodule #(parameter DEPTH=16, WIDTH=8) (...) // commas between
> >all parameter assignments / only one parameter keyword
> >
> >(6) module mymodule #(parameter DEPTH=16, WIDTH=8;) (...) // commas
> >between all parameter assignments / only one parameter keyword
> >
> >(7) module mymodule #(parameter DEPTH=16, AWIDTH=8; parameter BWIDTH=8)
> >(...) // commas between parameter lists but a semicolon to separate
> >another parameter keyword in the list
> >
> >(8) module mymodule #(DEPTH=16, AWIDTH=8, BWIDTH=8) (...) // commas
> >between parameter assignments but no parameter keyword / the #(...) syntax
> >indicates parameters
> >
> >(9) module mymodule #(parameter AWIDTH=8, BWIDTH=8; localparam
> >YWIDTH=AWIDTH+BWIDTH; parameter DEPTH=16) (...) // mixture of semicolon
> >separated parameter and localparam declarations
> >
> >(10) module mymodule #(parameter DEPTH=16, AWIDTH=8, BWIDTH=8; localparam
> >YWIDTH=AWIDTH+BWIDTH) (...) // both parameters and localparams permitted
> >but all localparams must follow all parameter declarations
> >
> >(11) module mymodule #(DEPTH=16, AWIDTH=8, BWIDTH=8; localparam
> >YWIDTH=AWIDTH+BWIDTH) (...) // both parameters and localparams permitted
> >but all localparams must follow all parameter declarations. Parameter
> >keyword not required.
> >
> >(12) module mymodule #(parameter DEPTH=16; localparam
> >AWIDTH=clogb2(DEPTH)) (...) // both parameter and localparam permitted.
> >All localparams must follow all parameter declarations. The localparam
> >calls the ceiling of the log-base-2 (clogb2) constant function to
> >calculate the address width (AWIDTH) for the specified DEPTH.
> >
> >(13) module mymodule #(DEPTH=16; localparam AWIDTH=clogb2(DEPTH)) (...) //
> >both parameter and localparam permitted. All localparams must follow all
> >parameter declarations. The parameter keyword is not required. The
> >localparam calls the ceiling of the log-base-2 (clogb2) constant function
> >to calculate the address width (AWIDTH) for the specified DEPTH.
> >
> >I believe the following is true:
> >
> >Legal per the BNF: (3) (6)
> >Illegal per the BNF: (1) (2) (4) (5) (7) (8) (9) (10) (11) (12) (13)
> >
> >Legal per the documentation (see first example of section 12.2): (5)
> >Intended legal per the documentation(??): (1) (7)
> >Not legal per the documentation (no known examples in the Standard): (2)
> >(3) (4) (6) (8) (9) (10) (11) (12) (13)
> >
> >Cliff would like these to be legal: (1) (5) (7) (8) (10) (11) (12) (13)
> >(The #(...) notation and adding the keyword parameter now seems to be
> >redundant)
> >Cliff does not want these to be legal: (2) (3) (4) (6) (9)
> >
> >Legal(by mistake?) (but Cliff would not like these to be legal): (3) (6)
> >
> >I would like to see opinions from other BTF, VSG and SystemVerilog
> >participants.
> >
> >I wish I had been more thorough about parameters and localparams during
> >the IEEE process.
> >
> >Regards - Cliff
> >//*****************************************************************//
> >// Cliff Cummings Phone: 503-641-8446 //
> >// Sunburst Design, Inc. FAX: 503-641-8486 //
> >// 14314 SW Allen Blvd. E-mail: cliffc@sunburst-design.com //
> >// PMB 501 Web: www.sunburst-design.com //
> >// Beaverton, OR 97005 //
> >// //
> >// Expert Verilog, Synthesis and Verification Training //
> >//*****************************************************************//
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Stuart Sutherland Sutherland HDL Inc.
> stuart@sutherland-hdl.com 22805 SW 92nd Place
> phone: 503-692-0898 Tualatin, OR 97062
> www.sutherland-hdl.com
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>



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