Subject: Re: Keyword Caution (was: keyword 'cell')
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Nov 29 2001 - 10:15:50 PST
At 11:46 AM 11/29/01 -0600, Adam Krolnik wrote:
>Good morning;
You always start with these controversial statements! How do you know it is
a good morning?! ;-)
>One thing worth noting. The reserved word 'cell' is only used in the
>context of
>a configuration block. If context sensitive parsing wasn't so abhored we
>could have
>indicated that this word would be acceptable within modules.
True. But as Paul pointed out, I think he is working with some designs
where the engineers chose the module name of cell.
>Cliff, I maybe the only one missing this, but what proposal is asking
>for a new
>type named 'state'?
This is part of the Accellera System Verilog donation from Co-Design.
Vassilious - I went to the eda.org web page and saw nothing on HDL+ or
SystemVerilog. I followed the links to Accellera and Technical Activities.
On this page, there is a reference to HDL+ but no link or additional info.
We seem to be a stealth group!
Adam - FYI - System Verilog is divided into two main groups, language
enhancement and verification enhancement. I have only been peripherally
watching the verification enhancement efforts, largely driven by co-chairs
John Emmit of Verplex and Tom Fitzpatrick of Co-Design. Harry Foster now
with Verplex was a co-chair and is still a very active participant (I think
he had to resign as co-chair after joining Verplex because it would not
look right to have co-chairs from the same company). The language portion
is co-chaired by Vassilios and Dave Kelf of Co-Design. I am a very active
participant on the latter.
The goal is to have a working Accellera spec by DAC and then to take that
through the more rigorous IEEE process after that. Exciting design and
verification enhancements are in the works. You should join one or both groups.
Hope this helps.
Regards - Cliff
> Adam Krolnik
> Verification Mgr.
> LSI LOgic Corp.
> Plano Tx. 75074
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