Subject: Re: "universal" logic type
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Wed Jan 23 2002 - 15:07:10 PST
> From: "Alec Stanculescu" <alec@fintronic.com>
> To: stefen@boyd.com
>
> >
> > At 10:31 AM 1/21/2002 -0800, Alec Stanculescu wrote:
> > >Question: what is the advantage of not giving a special name (wire or
> > >reg) to a an object which we know will be used in a certain way. The
> > >more information we can capture in a declarative way the better of we
> > >are (in general:-).
> >
>...
>
> I agree with you that more thought ought to be given to this issue.
> First I propose, as Peter suggested, to separate the issues of value
> of object and other properties such as resolution function, and
> context in which it can be assigned from.
>
> Second, we should enumerate perceived problems with these objects.
>
> 1. Peter rephrased Stefen's complaint into "why can't write into a reg
> from a continuous assignment?" Do you agree with this restatement
> Stefen?
>
> 2. Personaly, I do not like the fact that a reg is not a register for
> synthesis purposes. I believe that there should be objects called
> 2.1 wires that have resolution functions associated with them,
> 2.2 variables (this is present in VHDL) which do not have resolution
> functions associated to them(or a resolution function that resolves
> to the latest value driven by any of the drivers).
> 2.3 registers which do not have resolution functions associated to
> them and which should be synthesized as registers. They should have
> a predefined operation reset to a specific value and should allow
> the clock to be specified in their declaration. The reset operation
> is asynchronous as opposed to all other assignments that are
> synchronous with the declared clock (posedge or negedge as declared).
>
> Multiple clocks associated to one reg could be supported as well.
>
> All objects (wires, var, and reg) can be written from both continuous
> and procedural assigns. The values that these objects have are:
> wire - same as in Verilog
> var - 0, 1, x, z
> reg - 0, 1, x, u (where u is uninitialized and is otherwise the same
> as x).
>
> I understand that the Verilog legacy may not allow us to do this, but
> I am trying to understand better what it is that we should want.
I think it being 'reg' predates synthesis somewhat and shouldn't be
confused with the synthesis usage as a register. It is just a syntactic
mechanism which allows multiple threads (processes/always-blocks) to
share a driver (which isn't possible with VHDL), and is a feature that
makes Verilog more efficient at modelling some logic circuits. Processes
that write to a net as a 'wire' have an implicit (unshared) driver.
Resolution is only required when there are multiple drivers, i.e. the
value written to a 'reg' is only guaranteed to be the value of the net
when it is the only driver.
On reflection, the missing syntax/semantic is probably something that
lets you share a 'reg' (driver) to sub-modules so that the sharing is
limited, and such that it is still possible to mix that usage with regular
gate/RTL blocks. E.g. use 'logic' to inherit a driver from a parent or
to create an equivalent 'reg':
module foo;
reg a;
bar (a);
endmodule
module bar(a2);
output a2;
logic a2; // use driver for 'a' above
initial a2 = 0;
endmodule
I think that has the advantages of efficiency and backward compatibility.
Kev.
This archive was generated by hypermail 2b28 : Wed Jan 23 2002 - 18:09:26 PST