Subject: Clean up items to sections 8 and 10
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Thu Mar 28 2002 - 13:35:44 PST
All,
The following comments describe several items of cleanup to draft 4 section
8 and 10 that I have made in draft 5. I skipped over section 9 on FSMs,
because there is still too many pending changes. My e-mail dated 25 Mar
2002 covers clean up actions in section 1 to 7.
1. Draft 4, Section 8.1, Introduction:
The 5th paragraph reads: "SystemVerilog adds C-like break and continue
functionality, ...". The return keyword should be added to the list.
2. Draft 4, Section 8.2, Blocking and nonblocing assigns:
The last sentence of the 3rd paragraph reads: "Nonblocking assignments to
automatic variables are not allowed." This is a separate topic from the
beginning of the paragraph, and should be it's own paragraph, probably
before the 3rd paragraph.
3. Draft 4, Section 8.2, Blocking and nonblocing assigns:
The 3rd paragraph says "...a warning is given." The IEEE wording does not
allow "is", and instead requires "shall" or "can" for required or
optional. I assume a warning in this case is optional, and the sentence
should end with "...a warning can be given."
4. Draft 4, Section 8.3, Selection assignments:
The first two examples do not have a lead-in paragraph to set the context
and intent of the examples. The examples really don't tell anything,
anyway. I suggest the examples be deleted.
5. Draft 4, Section 8.3, Selection assignments:
The first paragraph does not explain how SystemVerilog differs from
Verilog. I suggest the sentence be changed from:
"The condition is evaluated as a boolean so that 0 or X or
null or void or {} are false and any other values are true."
To:
"In Verilog, an 'if (expression)' is evaluated as a boolean,
so that if the result of the expression is 0 or X, the test
is considered false. With SystemVerilog, null or void or {}
are also false."
6. Draft 4, Section 8.3, Selection assignments:
The 2nd sentence of the 2nd paragraph reads: "In the case of an else...if,
the unique indicates that the conditions do not overlap." This is
redundant with the 3rd paragraph. I suggest it be struck from the 2nd
paragraph.
7. Draft 4, Section 8.3, Selection assignments:
The 2nd, 3rd and 5th paragraphs say a warning "is" given. In these
paragraphs, I assume a warning is required, and should say "shall be".
8. Draft 4, Section 8.3, Selection assignments:
In the priority if example, I suggest the following comment be added to the
final else, For clarification: "//covers all other possible values, so no
warning".
9. Draft 4, Section 8.3, Selection assignments:
The third paragraph that begins with "In the case of the unique if..." is
awkwardly worded. I suggest the paragraph be split into two, and reworded
as follows:
"A unique if indicates that there should not be any overlap
in a series of if...else...if conditions, allowing the
expressions to be evaluated in parallel. A software tool
shall issue an error if it determines that there is a
potential overlap in the conditions."
"A priority if indicates that a series of if...else...if
conditions shall be evaluated in the order listed. In the
preceding example, if the variable 'a' had a value of 0,
it would satisfy both the first and second conditions,
requiring priority logic."
10. Draft 4, Section 8.3, Selection assignments:
The 4th paragraph that begins with "In Verilog-2001, there are three
types..." should be combined with the 5th paragraph.
11. Draft 4, Section 8.3, Selection assignments:
The last sentence of the 5th paragraph says "The user does not need to
code...". I suggest this be more professionally worded as "By specifying
unique or priority, it is not necessary to code...".
12. Draft 4, Section 8.7, Named blocks and statement labels:
The 2nd paragraph ends with "It is an error if the name at the end is
different." Different than what? The following should be added to the end
of the sentence: "than the block name at the beginning".
13. Draft 4, Section 8.7, Named blocks and statement labels:
The 5th paragraph ends with "It is an error if the label at the end is
different." Different than what? The following should be added to the end
of the sentence: "than the label at the beginning".
14. Draft 4, Section 8.10, Delay and event control:
The first paragraph reads: "SystemVerilog has #time or #(time_expression)
as a delay control, like Verilog-2001.". There is nothing new here. The
paragraph should be deleted, and "Delay and" struck from the section title.
15. Draft 4, Section 8.10, Delay and event control:
The 2nd paragraph reads: "SystemVerilog adds the following
enhancement:". There is no lead-in explanation. Suggest taking the first
sentence of the 5th and 6th paragraphs, and making them the lead-in
discussion, and changing the 2nd paragraph to: "SystemVerilog adds an iff
qualifier to the @ event control."
16. Draft 4, Section 8.10, Delay and event control:
The second sentence of the 5th paragraph begins with: "For more clarity,
SystemVerilog also allows the event control...". After change 15, this
will become the 1st sentence, and should be modified to begin with:
"SystemVerilog also allows the @ event control..."
17. Draft 4, Section 8.10, Delay and event control:
The 4th paragraph references a "dense" array. I assume this should be a
"packed" array.
18. Draft 4, Section 8.10, Delay and event control:
The 6th paragraph covers two topics. It should be split at the sentence
that begins with: "SystemVerilog allows assignment expressions...".
19. Draft 4, Section 10.1, Introduction:
The 1st sentence of the 2nd paragraph, reads: "SystemVerilog adds
specialized always_comb and always_latch blocks are provided". The words
"are provided" should be struck.
20. Draft 4, Section 10.1, Introduction:
The 2nd paragraph, which begins: "In an always block which is used to model
combinational logic...", there is no mention always_ff blocks, or that the
special blocks affect simulation as well as synthesis and formal
verification. Suggest adding "simulation" to the first sentence, and
adding after the first sentence: "SystemVerilog also adds an always_ff
block to indicate sequential logic".
21. Draft 4, Section 10.1, Introduction:
The last 2 sentences of the 2nd paragraph, beginning with: "These blocks
treat functions calls..." are currently under debate. The rule is also
repeated in the normative text of section 10.3, where it belongs. I
suggest these sentences be deleted from the introduction.
22. Draft 4, Section 10.1, Introduction:
The 1st sentence of the last paragraph, beginning with: "When dynamic
processes are created..." conflicts with section 10.7 that says dynamic
processes cannot be deleted. Suggest deleting this sentence, and moving
the 2nd sentence to the normative description of process labels in section
10.2.
23. Draft 4, Section 10.2, Static process labels:
Per the previous item, the 1st paragraph should be reworded as: "In
SystemVerilog, static processes can be named by labeling the outermost
statement. A label before the process statement serves as an identifier of
the process. This process identifier can be used to refer to variables
within that process."
24. Draft 4, Section 10.2, Static process labels:
The section title "Static process labels" could mislead readers to think
that dynamic processes cannot have labels. Suggest striking the word
"static" from the title and first paragraph.
25. Draft 4, Section 10.2, Static process labels:
This section seems too far removed from section 10.7 on dynamic
processes. Suggest moving 10.2 to 10.6.
26. Draft 4, Section 10.6, Continuous assignments:
The 2nd sentence begins with: "In SystemVerilog, continuous assignments can
drive..". This could be reworded to be more clear on what SystemVerilog
enhances. Suggest making the 2nd sentence a new paragraph, and rewording
as: "SystemVerilog removes this restriction, and permits continuous
assignments to drive...".
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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