Subject: Minutes Verilog++ 8th committee meeting
From: Simon J. Davidmann (simond@co-design.com)
Date: Mon Sep 24 2001 - 10:33:22 PDT
Verilog++ 8th committee meeting - Simon as minute taker.
September 24th, 2001
Attendees
(aaaaaaaa) Vassilios Gerousis *
(rar-aaaa) Dave Kelf * (Matthew Hall)
(aa--aaaa) John Sanguinetti *
(-ra-aaa-) John Emmitt
(-a-aa---) Dennis Brophy
(aaaaaaaa) Stu Sutherland *
(---aaaaa) David Knapp
(aaar-aaa) Tom Fitzpatrick *
(aaaaaaa-) Phil Moorby *
(aaaaaaaa) Anders Nordstrom *
(a-aaaaaa) Cliff Cummings *
(a-aaaaaa) Simon Davidmann *
(--aaaa--) Harry Foster
(a-a-a-aaa) Stefen Boyd *
(aaaaaaaa) David Smith *
(a-a--aa-) Mike McNamara *
(a) Kevin Cameron *
(a) Andy Tsay *
Attendance record key
a = attended, r = representative sent, - = not present
* beside name means attended this meeting - to make it more obvious
MOTION:
------------
"move that we accept the Co-Design donation of SUPERLOG ESS as the starting
point for developing a set of Verilog extensions"
9 people eligible to vote
proposed Stu
2nd Cliff
passed unanimously (Vassilios as chairman, not vote)
Discussion
-----------------
Suggest quick review of new document in next 4 weeks, and fix most issues,
with list of major outstanding issues.
We need this list of issues to resolve
Process to Standardization
Accellera standard approved and document published
(should not need paperwork to get approval from IEEE to reference IEEE
Verilog spec)
(as it references IEEE Verilog, (and not includes all IEEE Spec), then
there is no problem just to reference)
(might need IEEE permission to reproduce BNF and add to it)
Donation to IEEE: IEEE working group 1364 awakens from hibernation -
expect 6 months from now - same people from before
Assertions:
Would like input from Accellera Assertions sub-committee on where they are
as to donations and their timelines
Missing from IEEE Verilog2001
enum, structs, ptrs - SUPERLOG does address them all, and ESS only covers
enum, structs.
Simon explained that at some stage Co-Design could donate ptrs and other
Architectural features - but lets get this lot sorted first - finish what
is on plate before having seconds....
Discussion on Names:
-----------------------
Stu ESLD name - not really liked - nor is ESS.
It is a Verilog++ committee...
ideas - Accellera Verilog Extensions (AVEnue to the future....)
Verilog ACcellera Extensions (Verilog ACE) (Simon's suggestion)
needs acceptance in user community (subset name does not feel good - so
cannot be used)
QUESTIONS:
Discussion on Logic/regs/wires - not yet resolved - Cliff
---------
Implicit Wires (Peter F and David Smith to discuss)
-----------------
David Smith (implicit wires - hooks to AMS from in Interfaces?) was writing
document and sent around - people need to look at it and - currently no
decision.
There are several positions
Question - is there a real problem, and do we understand it and do we want
to address it.
ISSUES:
Interface section: - PeterF/Tom/Cliff
-----------
Need an elaboration on the Interface section, and need some of the examples
putting back - that show tasks/functions in Interfaces.
PeterF/TomF ----- still working on Interface section - need to work on
- Maybe Cliff can help and then get to Stu
Could this be the one that Stefen Boyd wrote?
Needs a more comprehensive example.
Using BNF from IEEE Verilog with extensions for ESS in Accellera standard
document - Vassilios
-----------
Vassilios --- to ensure paper work is completed to allow Accellera
document is OK with the use of BNF extended from the IEEE Verilog spec.
Issue List - Stu
-----------
extract the list of issues and status summary from the current document and
circulate
(next meeting we will assign to individuals to resolve these issues)
PLAN going forward
-------
NEXT MEETING 9 AM pst 8th Oct - 405 244 5555 code 3715
think on name of this ESS as an Accellera standard.
complete actions above
think on implicit wires
review draft 1 before next meeting
Future meetings
22nd Oct
5th Nov
face 2 face in Nov 12th -
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