Subject: Minor clean up questions, sections 1 to 7
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Mon Mar 25 2002 - 08:47:08 PST
All,
I've been working on creating an index for the SystemVerilog LRM. In the
process of doing so, I've come up with several questions. Most should be
quick to answer, but may require adding a sentence or two to the LRM so
that the questions are answered for all readers.
1. Draft 4, Section 3.8 Casting:
All examples show parenthesis around the cast operation. Are parenthesis
required? What is the precedence of a cast operation?
2. Draft 4, Section 3.8 Casting:
The last example in the section begins with:
typedef bit [$bits (tagged) - 1 : 0] tagbits; //tagged defined above
The comment refers to a declaration in a previous section. I'd like to
copy that definition to be part of this example. OK?
3. Draft 4, Section 4.4 Multiple dimensions:
The last paragraph begins with:
"If an index expression is of type logic vector, ..."
The phrase "of type logic vector" appears several times in the
paragraph. Is it really just that data type that these rules apply to, or
is it any 4-state data type? If the latter, than I suggest changing the
wording to "a 4-state vector" or "a 4-state value"
4. Draft 4, Section 4.4 Multiple dimensions:
The last paragraph says in two places:
"an X in the index expression will ..."
What if the index contains a Z? I assume the same rules apply. Can I
change the sentence to be "an X or Z in the index expression..." in both
places?
5. Draft 4, Section 5.3 Constants:
The last paragraph says to refer to section 14 for parameter
declarations. Section 14 is not very long. I suggest moving all of
section 14 to section 5.3, and deleting section 14.
6. Draft 4, Section 7.1 Introduction:
The third paragraph that begins with "Verilog-2001 added signed nets and
registers..." This paragraph is stating that SystemVerilog follows the
Verilog-2001 rules. This seems like it should be in the normative text,
rather than in the informative introduction. Can I move this paragraph to
section 7.7?
7. Draft 4, Section 7.1 Introduction:
The last paragraph doesn't say anything about SystemVerilog enhancing
Verilog. If there is nothing new, then I propose this paragraph and
example be deleted. The SystemVerilog LRM should only be providing regular
Verilog rules and examples as background for what SystemVerilog enhances.
8. Draft 4, Section 7.3 Assignment, incrementor and decrementor operations:
The last sentence reads "Assignment operators may only be used with
blocking assignments." The sentence is in a paragraph about assignments in
expressions, but seems to be a blanket rule for all assignment
statements. If the rule applys for all types of assignment statements
using assignment operators, then that sentence should be to a separate
paragraph. If the rule only applies to assignment operators in
expressions, then the wording should be changed to "Assignment operators in
expressions..."
9. Draft 4, Section 7.4 Operations on logic and bit types:
The 4th, 5th and 6th paragraphs talk about short circuiting. Are these the
same rules as Verilog? If so, then the paragraphs and examples should be
removed. If the rules are different, then an explanation is needed on how
they are different.
10. Draft 4, Section 7.5 Real operators:
Are the second paragraph and list of operators different than Verilog
rules? If so, the difference should be explained. If not, then the
paragraph should be changed to "SystemVerilog real and shortreal types have
the same restrictions on operations as Verilog real types".
11. Draft 4, Section 7.6 Size:
The last paragraph that reads:
"A tool may warn when the left and right hand sides of
an assignment are different sizes. These warnings can
be prevented by using casts."
Is the intent to say tools may generated the warnings, or to explain the
advantage of SystemVerilog size casting over Verilog? If the latter, then
I suggest the paragraph be changed to:
"With Verilog, some tools may issue a warning when the
left and right hand sides of an assignment are different
sizes. Using the SystemVerilog size casting, these
warnings can be prevented."
12. Draft 4, Section 7.9 Concatenation:
The second paragraph needs a lead in explanation. I haven't thought out
what to say yet. Any one have a suggestion?
13. Draft 4, Section 7.9 Concatenation:
The example after the second paragraph reads:
bit [1:0] packedbits = {1,1}; //right hand side is 64 bits
This would be an illegal concatenation in Verilog, which does not allow
unsized numbers in concatenations. Is this a new feature in
SystemVerilog? If so, it needs to have a separate paragraph explaining the
feature. The BNF needs to reflect the capability as well.
14. Draft 4, Section 2 Lexical conventions:
(OK, so I jumped back to the beginning--my random access memory works very
randomly). The section title is "Lexical conventions", but the entire
section is about literal values. Can I change the name of the section to
"Literal values".
That's it for now. I'm still working on indexing sections 8 and on, and
will probably have a few more odds and ends for then.
Stu
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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