Re: globals and name searching

Subject: Re: globals and name searching
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Thu Mar 21 2002 - 19:41:36 PST

Peter,

The reference to section 12.5 appears to be in the Verilog-2001 LRM, not the SystemVerilog LRM.  I cannot add anything to the Verilog-2001 LRM.  I've tried to capture your intent by adding the following paragraph to the end of section 12.2 of the SystemVerilog LRM, draft 4:

When an identifier is referenced within a scope, SystemVerilog follows the Verilog-2001 upward searching rules until the root of the hierarchy is reached, and then searches in the $root global name space. An identifier in the global name space can be explicitly selected by pre pending $root. to the identifier name. For example, a global variable named system_resetcan be explicitly referenced using $root.system_reset

Did I get it right?

Stu

At 08:46 AM 3/20/2002, Peter Flake wrote:
Stu,

I would suggest changing 12.5 para 1 to say "until the root of the hierarchy is reached, and then in the $root global name space".

And then later add
        d) Look in the $root global name space.

A name in the global name space can be explicitly selected as $root.myname.

Peter.

At 10:44 PM 3/19/02 -0800, Stuart Sutherland wrote:

In March 18th's phone conference, I expressed concern that Verilog's rules for upward name searching might conflict with referencing globals.  I've reviewed the SystemVerilog and Verilog-2001 LRM's, and still feel a clarification is needed.  The attached PDF file shows the name search rules, as defined in the 1364-2001 standard.  It seems indicate that under some circumstances, name searching can extend beyond the module boundary into parent modules within the hierarchy.  In the draft 4 SystemVerilog description of the $root global name space (section 12), I do not find any explanation on when a name will be searched for in the global space.  When does the searching switch from Verilog's upward searching to looking in the global space?

The name search rule for globals needs to be defined, and in such a way as to be compatible with the Verilog-2001 standard's name search rules.  Can someone propose wording for the SystemVerilog LRM for global name searching?

Stu


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland                                  Sutherland HDL Inc.
stuart@sutherland-hdl.com                          22805 SW 92nd Place
phone: 503-692-0898                                Tualatin, OR 97062
www.sutherland-hdl.com
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland                                  Sutherland HDL Inc.
stuart@sutherland-hdl.com                          22805 SW 92nd Place
phone: 503-692-0898                                Tualatin, OR 97062
www.sutherland-hdl.com
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

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