Subject: Re: Official Issue List for SystemVerilog 3.1 and comments
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Jun 03 2002 - 10:09:48 PDT
> Hello Everyone,
> I have copied Verilog++ SystemVerilog 3.0 issue list From David Kelf. This is our official list, any new one will be presented discussed and voted on to be part or rejected from the official list for 3.0.
>
> a. Deprecation follow on
> b. Time precision and timescale in general
> c. Data Channels
> d. Pointers
> e. Force Release extensions for strength etc
> f. State Machines
> g. Extern modules
> h. Object Orientation
> i. Datapath enhancements
> j. Interfacing to "foreign" languages - e.g. VHDL and C/C++
> k. Alias capability
> l. Inheritance and Inferred Declarations
> m. Hierarchical and multi-clock FSMs
> n. Dynamic process naming and control
> o. API/PLI/C-interface
> p. Temporal Logic.
> q. Alternative to declaring (or not) one bit regs, regs in general, etc.
> r. DSM issues.
>
> David Lacey/Tom Fitz, could you please add to this the SystemVerilog Issue List.
>
>....
"Data alignment and packing" seems to have disappeared as an issue, since you can't do C style
pointers (and unions) without knowing how data is laid out, you might want to add it in again.
Regards,
Kev.
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