Subject: RE: HDL+ June 2002 Minutes - Modified
From: Vassilios.Gerousis@Infineon.Com
Date: Wed Jun 19 2002 - 23:39:38 PDT
Hello Stuart,
HDL+ was created to provide an umbrella for several sub-committees, including VHDL to be formed to address the future evolution of HDL. Verilog++ was created primarily to address co-design donation which is the synthesible subset of Superlog. Assertion was added from day one, as a vision to include as part of what is now SystemVerilog. Verilog++ did not analyze or debate the assertion. As we started to address a bigger picture we have created three new committees. How these are organized are my responsibility to get a better focus. The tasks that we have done in Verilog++ has been distributed to four sub-committees under HDL+. Each of those subcommittees need to address its area of responsibility and provide a deliverable to the Accellera board for standardization. As of June 5th, Verilog++ has no deliverable and no task to be performed.
We plan to discuss this in the meeting of HDL+ subcommittee chairs, which you were invited to.
We need to be flexible of how to organize and also how to work. Just keeping a committee that will not produce a deliverable is a waste of time.
I can keep it around if you want it. There is no plan for it to produce.
Thanks to Simon and his insistence that the board examine the voting composition, we cannot do a vote. Simon has pushed the board to review
the voting composition, and as such has exposed the fact that non-Accellera members especially the IEEE members have been allowed to vote. All voting members must be an associate member or higher. Until I can hear from the board, I must follow the board decision not to allow any exceptions.
Vassilios
-----Original Message-----
From: Stuart Sutherland [mailto:stuart@sutherland-hdl.com]
Sent: Thursday, June 20, 2002 8:02 AM
To: Vassilios.Gerousis@infineon.com; vlog-pp@eda.org; assertion@eda.org
Subject: RE: HDL+ June 2002 Minutes - Modified
ATTENTION: MOTION FOR VOTE FOLLOWS!
Vassilios,
Your statement that we, the HDL+ committee, decided to dissolve the Verilog++ committee during the 5 June 2002 HDL+ committee meeting is not correct. I was present, in person, for the entire 8 hour HDL+ meeting. At no time did I hear any discussion of dissolving the Verilog++ committee. This observation is collaborated in the minutes, which contain no record of such a discussion. The discussion was to create subcommittees within the Verilog++ committee, in order to more quickly review and develop road maps on what should go into SystemVerilog 3.1.
I did not, do not, and will not vote in favor of, or endorse in any way, any motion to break the overall definition for SystemVerilog 3.1 into multiple, disparate committees. It only makes sense to me to keep the definition of SystemVerilog under a single committee--the Verilog++ committee that defined it to begin with. Subcommittees under that single parent make sense. Disparate committees with no parent would be a mistake.
The error in the minutes on page 3 still stands. There is no "SystemVerilog Enhancement Committee". Therefore, as the minutes are currently worded, no subcommittees have been formed.
Accellera's committee rules require that all minutes be voted on and approved by the committee for which the minutes apply. Before these minutes can be approved, any errors noted must be corrected.
AS AN HDL+ COMMITTEE MEMBER AND AN IEEE 1364 REPRESENTATIVE, I MOVE FOR AN E-MAIL VOTE FROM ALL ELLIGIBLE HDL+ COMMITTEE MEMBERS TO CORRECT THE MINUTES OF THE 5 JUNE 2002 HDL+ MEETING AS FOLLOWS:
CHANGE THE MINUTES ON BOTTOM OF PAGE 3 FROM:
"Motion: Approve creation of the sub-committees for SystemVerilog Enhancement Committee..."
TO:
"Motion: Approve creation of the sub-committees for the Verilog++ Committee..."
IS THERE A SECOND?
In addition, there is another error in the minutes. The final result for the vote on page two on limiting SystemVerilog 3.1 to just basic cleanup issues does not match the votes recorded. The minutes currently read:
"Proposal: Should SystemVerilog be limited to the Basic bucket list only?
Vote: No - Verplex, Alec (IEEE), Stu (IEEE), Synopsys, Novas, Cadence, Mentor
Yes - Cliff (IEEE), Verisity, Co-Design
Abstain - Real Intent
Motion approved"
The tally, as I count it, is 7 No, 3 Yes, and 1 abstain, yet the minutes say the motion is approved. Are the "No" and "Yes" categories mislabeled, or is the recorded result of the motion incorrect? I will leave it to someone else to propose the correction to this error in the minutes.
The minutes also contain references to several documents as being part of the minutes, yet those documents are not attached. These references are:
page 1: "HDL+ Agenda (See published agenda)"
page 1: "Introduction (See attached slides from Vassilios)"
page 2: "SystemVerilog Committee Issues (See Vassilios' slides. Changes to the issues were updated live on his slides."
page 2: "Synopsys Proposal (See Janant's slides)"
The omission of these documents is another error that must be corrected before the minutes can be approved.
Stuart Sutherland
At 09:18 PM 6/19/2002, Vassilios.Gerousis@infineon.com wrote:
Hi Stuart,
Verilog++ as of the meeting we had on June 5 does not exist. This is the decision
that was taken in the meeting. This is not a mistake that need to be corrected.
Vassilios
-----Original Message-----
From: Stuart Sutherland [ mailto:stuart@sutherland-hdl.com <mailto:stuart@sutherland-hdl.com> ]
Sent: Wednesday, June 19, 2002 7:17 PM
To: vlog-pp@eda.org; assertion@eda.org
Subject: Re: HDL+ June 2002 Minutes - Modified
All,
There is an error in the minutes for the 5 June 2002 Verilog++ face-to-face
meeting. This error will need to be corrected before the minutes are voted
on and approved (Accellera's official rules require that minutes be
approved by majority vote).
The top of page three outlines the creation of three subcommittees:
"issues", "C/C++ and interfaces", and "other enhancements". At the bottom
of page three is the vote to actually create these subcommittees. The
wording in the minutes for the vote state that the subcommittees are to be
formed as "...sub-committees for SystemVerilog Enhancement Committee...".
The current wording in the minutes would for subcommittees of a committee
that does not exist. That would void the entire vote to form
subcommittees. The wording needs to be changed to "...subcommittees of the
Verilog++ committee...".
Vassilios, please send out corrected minutes before the vote to approve the
minutes.
Stu
At 10:48 PM 6/17/2002, Vassilios.Gerousis@Infineon.Com wrote:
>Hi Everyone,
> I have attached a PDF document of the minutes. I have added
>Stuart Sutherland Sorted list to the minutes.
>
>Best Regards
>
>Vassilios
>
>------------------------------------------------------------------------------------------------------------------------------
>Dr. Vassilios Gerousis Infineon Technologies
> DAT CAD, MchB
>Telephone: +49-89-234-21342 BalanSt. 73
>Fax: +49-89-234-23650 D-81541 Munich
>email: Vassilios.Gerousis@infineon.com Germany
>Site Map:
> http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73 <http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr.;HNR=73>
>----------------------------------------------------------------------------------------------------------------------------------
>
> <<HDL+June 5 2002Minutes.pdf>>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com <http://www.sutherland-hdl.com/>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com <http://www.sutherland-hdl.com/>
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