Subject: External module definitions proposal
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Mon Apr 01 2002 - 14:13:39 PST
The aim of the external module definition is to define the bottom
of a design hierarchy for a particular use - which may be modular
compilation or (say) system-level synthesis with "black box" IP.
Modules declared as external are not elaborated if no "non-external"
definition is seen, and they would never be considered as a top
when a non-external module is eligible (even if their own non-external
definition is seen).
An external module declaration is a module definition preceded by
'extern', and it can be any subset of the non-external definition
- i.e. if both are present in the source then there should be nothing
declared 'extern' that isn't in the full definition (with the exception
of attributes). This allows the following Verilog:
In file "library.v"
`ifdef EXPORT_ONLY
extern
`else
`ifndef DECL_ANALOG
`define DECL_DIGITAL
`endif
`endif
module lib_cell1(input a, output b); // common interface
`ifdef DECL_DIGITAL
wire a;
always (@a) begin ...
`endif
`ifdef DECL_ANALOG
electrical a,b;
analog begin ...
`endif
endmodule
In file "block1.v":
`define EXPORT_ONLY
`include "library.v"
`undef EXPORT_ONLY
module block1(...);
wire x,y;
lib_cell1(x,y);
...
In file "block2.v":
`define EXPORT_ONLY
`include "library.v"
`undef EXPORT_ONLY
module block2(...);
wire a,b;
lib_cell1(.*);
...
A command line to compile the lot would be:
sv-compile block1.v block2.v library.v
but both block1.v and block2.v would be considered "complete"
and independently compilable, which is important for block2.v
which uses the '.*' syntax.
Since the `extern` module has the same syntax as a regular
module few changes are required to the BNF. The Verilog tool
reading the source should check for compatibility between the
external definitions and the non-external, but that would not
be a strict requirement.
Notes:
1. I would rather use 'extern' than 'import' because I would
like to reserve the use of 'import' for picking the definition
from a specific library in future, e.g.:
extern module libX; endmodule // forward declare library module
import libX module cellY (...); // use cellY
endmodule // from module libX
2. Attributes in an external definition may be used to help
locate the actual definition or compiled code as needed.
3. Some mixed-signal simulators do extern/import externally to
the Verilog source and just leave stubs for the modules in the
digital Verilog, this does it formally (and portably).
Regards,
Kev.
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