Subject: Re: FSM Section Vote?
From: Stefen Boyd (stefen@boyd.com)
Date: Tue Apr 02 2002 - 16:56:15 PST
At 03:28 PM 4/2/2002 -0800, Clifford E. Cummings wrote:
>Did you get the message that we decided to conduct an email vote on the
>proposal to remove the FSM section from version 3.0 of the SystemVerilog
>Standard? I thought the Co-Design guys were going to ask you to conduct
>that vote and that voting would close on Friday, April 5th.
>
>PROPOSAL: Remove the State Machine Section (section 9 in draft 4) from the
>SystemVerilog draft standard.
>Proposed by: Cliff Cummings
>Seconded by: Stu Sutherland (is this correct Stu?)
Cliff,
Actually, I suggested that we defer the fsm section
to version 3.1 - which, I thought, you made into a
formal proposal. Although this also removes it from
3.0, it leaves it as an item for consideration. I'm
not ready to axe it from the standard yet. With your
wording for the proposal, I would vote no.
Stefen
--------------------
Stefen Boyd Boyd Technology, Inc.
stefen@BoydTechInc.com (408)739-BOYD
www.BoydTechInc.com (408)739-1402 (fax)
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