Subject: Fwd: RE: Cliff Cummings - FSM Proposals and models
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Sat Mar 02 2002 - 09:54:09 PST
>Date: Sat, 02 Mar 2002 09:27:55 -0800
>To: mac@verisity.com
>From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
>Subject: RE: Cliff Cummings - FSM Proposals and models
>Cc: "Clifford E. Cummings" <cliffc@sunburst-design.com>
>
>At 06:21 PM 3/1/02 -0800, Michael McNamara wrote:
>
>>You wrote:
>>-----------------
>>PROPOSAL: do not require begin-end for transition-endtransition
>>item-statements Note: I can live with begin-end but removing them
>>would be nice.
>>
>>Reasons:
>> (1) VHDL does not require begin-end inside of VHDL case
>> statements.
>>
>> Verilog does because a Verilog case item can be an expression,
>> making it more difficult to detect where a case-item-statement ends
>> and where a case-item-expression begins. I believe transition does
>> not permit expressions in the tested items, which should make
>> detection of the transition-item easier to find, even without the
>> begin-end pair.
>>-----------------
>>
>>
>>Verilog doesn't require begin end around case items! A case ietm is
>>defined as 'statement_or_null' which could include begin end, but
>>does not require them.
>>
>> Hence:
>>
>> case (A)
>>
>> 1: ;
>> 2: B = A;
>> 3: begin
>> C = A;
>> end
>> B:;
>> f(a,b,c):;
>> default:;
>> endcase
>>
>>is perfectly legal.
>>
>>Ref Section 9.5 of the 1264-2001 standard.
>>
>>-mac
>
>Mac is right. My explanation was unclear. A case item statement does not
>require begin-end if there is only a single statement as Mac has shown
>above and some of the examples that I sent also do not use begin-end where
>they are not needed.
>
>If a case item statement has two statements, then a begin-end pair is
>required for those case item statements, which means if you add a second
>line of code to a case item statement, you will actually have to add three
>lines of code: (1) begin, (2) the second statement, (3) end. VHDL types
>like to find examples with two statements per case item to show "how
>verbose Verilog is."
>
>Again, in the examples I sent, I have omitted the begin-end pairs form the
>case item statements that do not require them.
>
>I'm still semi-hoping that transition statements can be created without
>requiring begin-end pairs.
>
>Regards - Cliff
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