Subject: FSM Section Vote Results
From: Dave Kelf (davek@co-design.com)
Date: Fri Apr 05 2002 - 05:51:22 PST
Hi Everyone,
The results of the vote to remove the state machine section from the
current draft of the SystemVerilog documentation are complete, and the
result is that the proposal is approved - the section should be removed.
We need to discuss at the meeting on Monday what to do about reserving the
state keyword.
Here is the official count:
Results of Email Vote, Verilog++ Committee
Proposal: Remove the State Machine Section (section 9 in draft 4) from the
SystemVerilog 3.0 LRM, and defer transition statement and operators for
consideration in SystemVerilog 3.1.
Vote Tally:
Vassilios Gerousis Abstain
Dave Kelf YES
Dennis Brophy NO
Stu Sutherland YES
Tom Fitzpatrick YES
Anders Nordstrom Abstain
Cliff Cummings YES
Simon Davidmann YES
Peter Flake YES
Stefen Boyd YES
David Smith YES
Michael McNamara YES
Kevin Cameron YES
Andy Tsay Abstain
Alec Stanculescu Abstain
Paul Graham YES
thanks everyone
Dave
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