All DVCon U.S. Video Tutorials Now Available
Two new SystemVerilog-related video tutorials from DVCon U.S. 2016 are now available. The SVA Advanced Topics: SVAUnit and Assertions for Formal technical tutorial introduces advanced topics for assertion-based verification including SVAUnit and SVA for formal. It includes SVA planning, coding guidelines, SVAUnit (SVAUnit framework, self-checking tests, debug), and test patterns. The SystemVerilog-AMS: The Future of Analog/Mixed-Signal Modeling tutorial provides an introduction to the concepts underlying the upcoming SystemVerilog-AMS language standard. The tutorial covers requirements and areas of concern for the new standard, data types, the new nodetype, connectivity, hierarchy, adapters, power-aware, filtering, and other constructs.
Two additional video tutorials from DVCon U.S. 2016 are also available. Cut Your Design Time in Half with Higher Abstraction explains how to use SystemC to write synthesizable models at a higher level of abstraction than RTL. The UVM Tips and Tricks Plus Preparing for IEEE UVM provide a plethora of tips and tricks to alleviate the struggle of debugging UVM testbenches including both compile time and runtime tips.
Shrenik Mehta Receives 2016 Leadership Award
Shrenik Mehta is the recipient of the 2016 Accellera Leadership Award. The award was presented at the Design Automation Conference (DAC) during the Accellera breakfast and town hall meeting on Tuesday, June 7. The award recognizes his vision, leadership and contribution to standards development, governance and promotional activities of the organization. Shrenik has more than 30 years of semiconductor and system industry experience. In addition to being a founding board member of the Accellera Organization in 2000, he was also vice chair from 2002-2005 and chair from 2005-2010. He is a current member of the Accellera Promotions Committee and an active participant in the Portable Stimulus Working Group. Shrenik helped guide several initiatives within Accellera that evolved into widely-used standards such as SystemVerilog, Unified Power Format (UPF) and Universal Verification Methodology (UVM). He was also vice chair of the IEEE 1800-2005 Standard for SystemVerilog Committee. In addition, Shrenik is member of the US Technical Advisory Group - ISO26262 TC32/SC22/WG8 Functional Safety Working Group. Read the press release >
- May newsletter now available
- Article: DVCon: Building a Community Through Quality Conferences
- Accellera Standards Technical Update video presentation
- System-Level Modeling for Today and Tomorrow with SystemC video presentation
- Article: DVCon U.S. 2016 Tackles Pressing Design and Verification Issues
- SCE-MI 2.3 released. Download | Read the press release
- New Portable Stimulus Working Group