Portable Stimulus Working Group Call for Contributions
The Accellera Portable Stimulus Working Group (PSWG) is pleased to announce that it is seeking contributions to assist in the creation of a Portable Test and Stimulus standard. The Portable Test and Stimulus standard will define a specification to permit the creation of a single representation, usable by a variety of users across different levels of integration under different configurations, enabling the generation of different implementations that run on a variety of execution platforms, including, but not necessarily limited to, simulation, emulation, FPGA prototyping and post-Silicon. Contributions will be accepted beginning on June 3, 2015 and ending on August 5, 2015. Find out more.
UVM in SystemC
UVM-SystemC development was initiated in a European project as part of the 7th Framework Programme, Verification for heterogeneous Reliable Design and Integration (VERDI), with the objective to develop a unified system-level verification methodology for heterogeneous systems. Much progress has been made since June 2014 when VERDI contributed the UVM-SystemC language reference manual (LRM) and reference implementation to Accellera for continued development. For more information about UVM-SystemC progress, read the new article, "Accellera’s UVM in SystemC Standardization: Going Universal for ESL." To get involved in the discussions, please visit the SystemC community and forum pages. To learn more, please view the video tutorial presented at DVCon US and view a technical paper by Martin Barnasconi, SystemC AMS Working Group chair.
- New Article: Accellera at DAC and Beyond
- Dr. Bill Read receives 2015 Accellera Leadership Award
- Article: Accellera’s UVM in SystemC Standardization: Going Universal for ESL
- May newsletter now available
- DVCon 2015 Panel Discussion: What is Needed to Drive Design Efficiency?
- New Portable Stimulus Working Group
- UVM 1.2 released. Download | Read the press release
- Verilog-AMS 2.4 released. Download | Read the press release