See Accellera at DAC
We are looking forward to an exciting Design Automation Conference (DAC) this year.
We invite you to join us at our Breakfast Panel and co-sponsored System Level Power Workshop.
Our breakfast panel, “Design and Verification Standards in the Era of IoT,” will bring together senior technologists from the IoT community to discuss the current status and future needs for standards cooperation in IoT. It will be in the Moscone Center, Room 220, on Tuesday, June 9 beginning at 7:30am. Register here.
The System Level Power Workshop, co-organized and sponsored by Accellera, the IEEE Design Automation Standards Committee (DASC) and Si2, will bring together members of both the user and standards communities to discuss the issues surrounding not only interoperability among tools and IP, but system level design and the creation of power models and their suitability at different levels of abstraction. It will be in the Moscone Center, Room 206, on Tuesday, June 9 from 1:15pm-4:30pm. Register here.
UVM in SystemC
UVM-SystemC development was initiated in a European project as part of the 7th Framework Programme, Verification for heterogeneous Reliable Design and Integration (VERDI), with the objective to develop a unified system-level verification methodology for heterogeneous systems. Much progress has been made since June 2014 when VERDI contributed the UVM-SystemC language reference manual (LRM) and reference implementation to Accellera for continued development. For more information about UVM-SystemC progress, read the new article, "Accellera’s UVM in SystemC Standardization: Going Universal for ESL." To get involved in the discussions, please visit the SystemC community and forum pages. To learn more, please view the video tutorial presented at DVCon US and view a technical paper by Martin Barnasconi, SystemC AMS Working Group chair.
Public Review of SystemC Synthesis Subset
The SystemC Synthesizable Subset Version 1.4 is now open for public review and comment until July 13, 2015. Community feedback on the draft is welcome for consideration in the next release of this standard. The document can be downloaded here. For more information and to submit feedback, please visit the Working Group’s public forum.
At DAC 2015
Jun 9, 2015
7:30am - 9:00am
Moscone Center, Room 220
San Francisco, CA
Sep 10-11, 2015
Nov 11-12, 2015
Subscribe to our mailing list:
- New Article: Accellera’s UVM in SystemC Standardization: Going Universal for ESL
- May newsletter now available
- DVCon 2015 Panel Discussion: What is Needed to Drive Design Efficiency?
- Justin Refice receives 2015 Technical Excellence Award
- New Portable Stimulus Working Group
- UVM 1.2 released. Download | Read the press release
- Verilog-AMS 2.4 released. Download | Read the press release