Technical Tutorials from DVCon Available
The complete set of technical tutorials from Accellera Day at DVCon 2015 is now available:
- SystemVerilog Design: User Experience Defines Multi-Tool, Multi-Vendor Language Working Set brings together leading edge technology users who have used SystemVerilog constructs in their design. They describe their motivations for using SystemVerilog, the successes and challenges they encountered, and the productivity gains achieved.
- Automating Design and Verification of Embedded Systems Using Metamodeling and Code Generation Techniques presents the application of the known software development methodology “Metamodeling and Code Generation” to the design of SOCs, mainly the semi-automated generation of SystemC prototypes, firmware and hardware (RTL, schematic) as well as verification.
- Next Generation Design and Verification Today explores how the SystemVerilog, UCIS, UPF, and other standards are applied in interesting ways to push the electronics industry.
- SystemC Standardization Update Including UVM for SystemC provides an update on the SystemC standard including analog modeling, a synthesizable subset, model-tool interface, and verification. It also includes an introduction to the Universal Verification Methodology in SystemC.
- Panel Discussion: What is Needed to Drive Design Efficiency? At the annual Accellera Luncheon at DVCon 2015, invited panelists discussed current practices in design efficiency as well as where standards need to go in order to fill gaps in efficiency.
UVM in SystemC
UVM-SystemC development was initiated in a European project as part of the 7th Framework Programme, Verification for heterogeneous Reliable Design and Integration (VERDI), with the objective to develop a unified system-level verification methodology for heterogeneous systems. Much progress has been made since June 2014 when VERDI contributed the UVM-SystemC language reference manual (LRM) and reference implementation to Accellera for continued development. For more information about UVM-SystemC progress, read the new article, "Accellera’s UVM in SystemC Standardization: Going Universal for ESL." To get involved in the discussions, please visit the SystemC community and forum pages. To learn more, please view the video tutorial presented at DVCon US and view a technical paper by Martin Barnasconi, SystemC AMS Working Group chair.
- New Article: DVCon India was a Great Success
- August newsletter now available
- SCE-MI 2.3 released. Download | Read the press release
- Dr. Bill Read receives 2015 Accellera Leadership Award
- Article: Accellera’s UVM in SystemC Standardization: Going Universal for ESL
- DVCon 2015 Panel Discussion: What is Needed to Drive Design Efficiency?
- New Portable Stimulus Working Group
- UVM 1.2 released. Download | Read the press release
- Accellera Systems Initiative Announces SCE-MI 2.3
August 20th, 2015
- Accellera Systems Initiative Delivers UVM 1.2 to IEEE for Standardization
July 30th, 2015
- Bill Read to Receive Accellera Systems Initiative Leadership Award
June 2nd, 2015